Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
1999-12-07
2001-01-23
Mai, Son (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S225500
Reexamination Certificate
active
06178111
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the field of electronic memory devices, and more particularly, to non-volatile storage devices.
Most digital electronic devices use both logic gates and memory elements to implement a desired function. The memory elements are used to store initial, intermediate and/or final data. The logic gates are used to provide and/or receive the data to/from the memory elements, and perform the necessary data manipulation. In a typical digital system, the basic memory elements are bi-stable logic circuits known as latching elements. There are numerous types of latching elements including, for example, D-latches, RS-latches, JK-latches, etc. These latching elements are often combined to form various forms of flip-flops, shift registers or other storage devices.
Latching elements typically use one or more feedback paths that have an even number of inversions. By providing an even number of inversions, the feedback path reinforces the stored data state of the latching element. To write a desired state to the latching element, the feedback path is typically overdriven or a switch is provided to temporarily interrupt the feedback path while a new data state is provided to the latching element. The most basic latching element includes a pair of cross-coupled inverters. There are, however, numerous other known implementations.
Conventional latching elements suffer from a number of limitations, some of which are described below. First, the initial state of a latching element is typically unknown. This limitation can cause a number of problems in a circuit or system. For example, the enable signal of selected output buffers is typically either directly or indirectly controlled by the state of a latching element. Because the state of the latching elements are unknown upon power-up, one or more of the output buffers may be simultaneously enabled. This is particularly problematic when the output buffers are coupled to a bi-directional bus, for example, where one buffer may attempt to overdrive another thereby drawing significant power and possibly causing damage to selected circuit elements.
To alleviate this and other problems, many systems require an initialization procedure to be executed shortly after power-up. One purpose of the initialization procedure is to initialize the state of selected latching elements. The initialization procedure may, for example, reset selected latching elements to disable the output buffers of a circuit or system. Generally, the initialization procedure initializes selected latching elements to prepare the device for subsequent processing. Requiring an initialization procedure increases the time required to boot the system.
Another related limitation of many conventional latching elements is that the data stored therein is lost when power is lost or otherwise interrupted. For example, when a personal computer or other data processing system loses power, the data stored in the latching elements are lost. When power is restored, the data processing system assumes an initial state that is unrelated to the state of the data processing system before the power loss. Often, much of the processing that was completed coincident with or prior to the power loss is lost, or must be re-constructed and/or re-executed which can be a time consuming and tedious task.
In high reliability applications, a primary power source and an auxiliary power source may be provided to reduce the likelihood that the latching elements will experience a power loss. In such systems, an auxiliary power source is used when the primary power fails. A limitation of this approach is that significant overhead is required including an auxiliary power source, a power degradation detection mechanism and a power switching mechanism. In addition, the auxiliary power source is often a battery or the like that has a limited lifetime. Therefore, if the primary power source fails for an extended period of time, the auxiliary power source may also fail causing the latching elements to lose the data stored therein.
A latching element that overcomes many of these limitations is disclosed in co-pending U.S. patent application Ser. No. 09/059,871, entitled “Non-volatile Storage Latch”, which is incorporated herein by reference. In one aspect, the referenced latching element senses the resistive state of one or more magnetic elements. By programming the magnetic elements to appropriate resistance values, the latching elements assumes a desired or known initial state upon power up.
SUMMARY OF THE INVENTION
The present invention is directed to means for efficiently writing desired states to one or more non-volatile latching elements that include one or more magneto-resistive elements. In one embodiment, the latching elements sense the state of a corresponding magnetic element pair. One of the magnetic elements of the magnetic pair is preferably written to a lower resistance state while the other magnetic element is preferably written to a higher resistance state. During a write, the latching element, which may be a cross-coupled inverter or the like, may sense the resistance differential of the magnetic element pair and assumes a corresponding logic state. The desired resistance state of any given magnetic element depends on the logic value that is to be stored in the latching element.
In accordance with one illustrative embodiment of the present invention, each magneto-resistive pair has a first local write line extending above a first magneto-resistive element and below the other, and a second local write line extending below the first magneto-resistive element and above the other. In this configuration, a write current passing through the first local write line may write the first magneto-resistive element to a low resistance state and the second magneto-resistive element to a high resistance state. Likewise, a write current passing through the second local write line may write the first magneto-resistive element to a high resistance state and the second magneto-resistive element to a lower resistance state.
Preferably, a number of magneto-resistive pairs are arranged in a string configuration with a first magneto-resistive pair at one end of the string and a last magneto-resistive pair at the other end of the string. In one embodiment, a current switch is provided between each magneto-resistive pair. The current switch for the first magneto-resistive pair preferably accepts a write current from a current source, voltage source, or the like, and switches the write current to either the first or second local write lines of the first magneto-resistive pair, depending on the state of a first write data signal. Each subsequent current switch preferably accepts an input write current from the first and second local write lines of an adjacent magneto-resistive pair, and switches the input write current to either the first or second local write lines of the corresponding magneto-resistive pair, depending on the state of the corresponding write data signal. In one illustrative embodiment, the first and second local write lines of the last magneto-resistive pair are connected to ground.
Each current switch may include an input terminal, a first output terminal, a second output terminal and a control terminal. The input terminal of the first current switch may be coupled to a current source or the like. The input terminal of the remaining current switches may be coupled to both the first and second local write lines of an adjacent magneto-resistive pair. The first output terminal of each current switch may be coupled to the first local write line of the corresponding magneto-resistive pair. The second output terminal of each current switch may be coupled to the second local write line of the corresponding magneto-resistive pair. The control terminal for each current switch is preferably coupled to a corresponding write data signal.
In this configuration, the first current switch accepts a write current from a current source or the like, and switch the write current to either th
Lu Yong
Sather Jeffrey Scott
Zhu Theodore
Fredrick Kris T.
Honeywell Inc.
Mai Son
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