Patent
1995-03-31
1998-06-30
Harvey, Jack B.
395487, G06F 300
Patent
active
057747458
ABSTRACT:
A computer system that has a bus is provided with a host memory coupled to the bus, this host memory having an event status queue in which events are stored. A peripheral controller is coupled to the bus and writes a termination marker in a first block in the memory and events occurring in the computer system in blocks in the event status queue in a first direction beginning with a block adjacent to the first block. A host processor is also coupled to the bus. The host processor reads the written events in a second direction opposite to the first direction beginning with a last block in which an event was written by the peripheral controller. The host processor terminates the reading of events when the first block in which the termination marker is reached. The use of a termination marker allows both the hardware of the peripheral controller and the software run by the host processor to operate in the event status queue at the same time, with no danger of running over each other.
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Cirrus Logic Inc.
Harvey Jack B.
Nguyen Frank D.
Wiley David A.
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