Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-07-14
2008-09-09
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185050, C365S185090, C365S185230
Reexamination Certificate
active
07423921
ABSTRACT:
A memory system including a memory array with redundant wordlines. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.
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Asano Toru
Dhong Sang H.
Nakazato Takaaki
Takahashi Osamu
Kahler Mark P
Luu Pho M.
Talpis Matthew B
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