Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-08
2001-10-30
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06311310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method and apparatus for circuit design (e.g., complementary metal oxide semiconductor (CMOS) circuit design) and to wiring integrated circuits (ICs), and more particularly to a method and apparatus for wiring ICs with multiple power buses based on performance.
2. Description of the Related Art
Conventional systems utilizing low power logic applications are growing rapidly as mobile communications (e.g., personal communications services, personal communication/data assistants, etc.) and pervasive computing become entrenched in modern society.
However, a dilemma faced by the integrated circuit (IC) designer is how to provide the computing performance to enable advanced features, such as voice recognition etc., while operating with a limited power supply (e.g., batteries). One solution is to provide high voltage power busing only for those circuits most critical for performance, and lower voltage power busing for less critical circuits.
However, this approach is problematic in that there is no method of determining how such power supplies should be optimally partitioned.
Further, there is a problem of crossing a low voltage logic path over to a path powered by higher voltages. Specifically, the problem is the inability of the lower output voltage to shutoff the transistor (e.g., PFET) load devices.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional systems and methods, an object of the present invention is to provide a structure and method for determining an optimal partitioning of a plurality of power supplies over an integrated circuit design.
Another object is to provide a circuit topology and method for overcoming the problem of crossing a low voltage logic path over to a path powered by higher voltages.
In a first aspect, a method according to the present invention for designing a circuit includes identifying paths in the circuit not satisfying preselected performance criteria, wherein identified paths are initially designed to be coupled to a first power supply, and redesigning the circuit such that the identified paths are coupled to a second power supply having a higher voltage than the first power supply, wherein the higher voltage is sufficient to increase performance of the identified paths such that they satisfy the performance criteria.
In a second aspect, an apparatus according to the present invention includes a plurality of devices, at least one of the devices having a first input and coupled to a first power supply for controlling an amount of current supplied to the apparatus from the first power supply, and a second input for receiving a signal from at least one low power signal path, the low power signal path coupled to a second power supply having a higher voltage than the first power supply, and wherein the at least one of the devices has an increased voltage threshold compared to others of the plurality of devices for minimizing an amount of current provided to the apparatus from the first power supply.
In another aspect of the invention, a method of optimizing performance and minimizing power dissipation of a plurality of integrated circuits, includes simulating the integrated circuits all wired with a first voltage power supply, identifying paths between the integrated circuits not meeting a delay margin criteria, wiring integrated circuits having paths not meeting the delay margin criteria with a second voltage power supply, determining and increasing a magnitude of load threshold voltages of all second voltage circuits having input signals emanating from first voltage bus circuits, re-simulating the integrated circuits and determining whether all logic paths meet delay margin criteria.
In other aspects of the invention, signal bearing media are provided for storing programs including the above-mentioned methods.
With the unique and unobvious structure and method of the present invention, performance can be optimized and power consumption can be minimized. Additionally, an efficient crossover of a low power voltage bus to a high power voltage bus may be performed.
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Bernstein Kerry
Ellis-Monaghan John Joseph
Rohrer Norman Jay
Chadurjian, Esq Mark F.
International Business Machines - Corporation
McGinn & Gibb PLLC
Phan Trong
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