Method and apparatus for wafer test of redundant circuitry

Details Method and apparatus for wafer test of redundant circuitry Method and apparatus for wafer test of redundant circuitry

1997-09-05

1998-11-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518902, 365200, G11O 760

Patent

active

058354310

ABSTRACT:
A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant rows/columns within a memory array during wafer test, without requiring permanent alteration of row/column select switches. Temporary enabling of redundant rows/columns allows testing of redundancy prior to alteration of the permanent switch logic. The control unit, upon command from a wafer tester, selectively enables particular redundant rows/columns to allow those redundant rows/columns to be tested. After testing, if the redundant rows/columns repair memory defects, permanent switch logic may be altered, without requiring further testing of the redundant circuitry.

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