Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-07-02
2001-03-20
Bragdon, Reginald G. (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S208000, C711S209000, C711S219000, C711S220000, C345S519000
Reexamination Certificate
active
06205531
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to virtual memory systems for computers and related devices. More specifically, the present invention includes a method and apparatus for translating virtual to physical addresses that provides simultaneous support for a wide range of memory uses.
BACKGROUND OF THE INVENTION
Modern computer systems typically provide some form of virtual memory environment. In an environment of this type, application processes (and in some cases, system processes) access memory using virtual addresses. The computer system is responsible for translating these virtual addresses into physical addresses within the memory of the computer system.
In a typical virtual memory environment, the virtual address space and the physical address space are both divided into fixed size pages. Each virtual address is a combination of a virtual page address and a page offset. Each physical address is a combination of a physical page address and a page offset. Using this system, page addresses may change during address translation, but page offsets remain the same.
The computer system maintains a set of data structures, known as page tables, for each process. The page tables provide a per-process mapping between virtual page addresses and physical page addresses. Translation of a virtual address is accomplished by using the page table to find the physical page address that matches the virtual address being translated. The page offset portion of the virtual address being translated is then added to the physical page address to form the complete physical address.
To provide adequate performance, computer systems using virtual memory typically cache recent translations between virtual and physical page addresses. In most cases, this type of caching is performed by a dedicated cache known as a translation lookaside buffer, or TLB. Use of a TLB dramatically speeds translation because repeated translations involving the same physical page address are performed without the use of page tables.
The performance benefit associated with the use of TLBs has made them indispensable components of virtually all computer systems where virtual memory is used. Still, it is generally the case that traditional TLB implementations have a number of limitations. One limitation is the inability of traditional TLBs to effectively manage systems that include a number of different page types. For example, a computer system may include pages that use linear addressing (where locations in memory are arranged as a linear sequence) and pages that use tiled addressing (where locations in memory are arranged as a number of rows). The same system may also include a number of different sizes for both tiled and linear pages.
Using different page types allows a computer system to optimize performance. Instructions and data that tend to be accessed in a linear fashion may be placed in linear pages. Specialized structures, such as frame buffers, that tend to be accessed on a row-by-row basis, may be placed in tiled pages. In each case, page sizes may be chosen to optimize performance and reduce memory fragmentation.
To use different page types effectively, a TLB must be able to cache translations to each page type. This is problematic because most TLB implementations are geared towards caching only a single type of translation. Effective use of different page types also requires that the TLB be able to separately manage each type. Separate management allows the computer system to prevent the TLB from being monopolized by translations to any particular type of page. Based on the foregoing, it may be appreciated that a need exists for TLB systems that allow for simultaneous use of a range of page types and sizes. A need also exists for systems that allow different page types and sizes to be separately managed.
SUMMARY OF THE INVENTION
The present invention includes a method and apparatus for efficiently translating virtual to physical addresses. A representative environment for the present invention includes a host computer system. The host computer system includes one or more host processors, a rendering engine and a system memory. The host processor and rendering engine access the system memory by sending requests to a memory request unit.
The memory request unit includes a TLB descriptor table that includes a series of TLB descriptors. Each TLB descriptor includes an offset that selects a segment within a translation lookaside buffer (TLB). To perform a virtual to physical address translation, the rendering engine or host processors send requests to the memory request unit. Each request includes a virtual address and a descriptor ID. The memory request unit uses the descriptor ID as an index into the TLB descriptor table. Using this index, the memory request unit selects a TLB descriptor from the TLB descriptor table.
The memory request unit then uses the offset included in the selected TLB descriptor to select a segment of the TLB. This segment is then examined to determine if it includes a physical page address for the virtual address being translated. If the selected TLB segment does not include a physical page address for the virtual address being translated, a TLB miss occurs. In this event, a host processor reloads the TLB to include the required physical page address. In either case, examination of the selected TLB segment generates a page address for the virtual address being translated.
The memory request unit then combines the physical page address with the page offset portion of the virtual address being translated. The result is a physical address that corresponds to the virtual address being translated.
Use of the TLB descriptor table allows the host processors to manage the TLB as a series of segments or sub-TLBs. Each TLB segment may have different physical and logical characteristics. This allows the same TLB interface to simultaneously support a wide range of different page types within the same system memory. Simultaneous support for different page types, such as tiled and linear memory of various tile and page sizes, enhances the flexibility and efficiency of the system memory. The use of the TLB descriptor table also allows the host processors to separately manage the sub-TLBs and the pages of system memory referenced by these sub-TLBs. This provides a better division of resources among the different uses of the system memory.
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description herein. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims and equivalents.
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Bragdon Reginald G.
Silicon Graphics Incorporated
Squire Sanders & Dempsey L.L.P.
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