Method and apparatus for verifying whether a bitstream received

Details Method and apparatus for verifying whether a bitstream received Method and apparatus for verifying whether a bitstream received

1994-11-23

1995-10-10

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 39, H03K 19177

Patent

active

054574080

ABSTRACT:
A field programmable gate array (FPGA) which verifies that an incoming bitstream is intended for it prior to writing configuration data to programmable memory cells is described. The bitstream has an identification frame which includes an identification code for the targeted FPGA. A verification circuit in a memory controller verifies whether the bitstream is intended for the FPGA based upon the identification code. If the bitstream is intended for the FPGA, the configuration data is processed and stored in the programmable memory cells. If the bitstream is not intended for the FPGA, the FPGA may enter a standby mode, and the configuration process may be halted until a user resets the FPGA. The verification circuit can help prevent damage that may occur to the FPGA when bitstreams intended for a different size memory cell array are received by the FPGA.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4642487 (1987-02-01), Carter
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5237609 (1993-08-01), Kimura
patent: 5311080 (1994-05-01), Britton et al.
patent: 5313520 (1994-05-01), Han
patent: 5347519 (1994-09-01), Cooke et al.

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