Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-10-04
2005-10-04
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S037000
Reexamination Certificate
active
06952795
ABSTRACT:
A control module (100) includes a first signal processing unit (102) that is coupled to a second signal processing unit (114) by a control bus (130), an address bus (131) and a data bus (132). The control module conveys seed value addresses (108) and expected result addresses (110) over the address bus, seed values (118) and verification set output values (107) over the data bus, and compares each verification set output value to an expected result (120), thereby allowing the control module to determine whether the first signal processing unit, the control bus, the address bus, and the data bus are collectively functioning correctly. By properly selecting the seed value addresses, expected result addresses, seed values, and expected results (and correspondingly, verification set output values), proper operation of each line of the address bus and control bus may be individually verified.
REFERENCES:
patent: 5668947 (1997-09-01), Batcher
patent: 6067586 (2000-05-01), Ziegler et al.
patent: 6647513 (2003-11-01), Hekmatpour
Ferrell Shawn
Grai Tim
O'Gorman Patrick A.
Bonura Timothy M.
Iqbal Nadeem
Mancini Brian M.
May Steven A.
Motorola Inc.
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