Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-02-18
2003-09-23
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000, C714S034000, C714S021000
Reexamination Certificate
active
06625759
ABSTRACT:
TECHNICAL FIELD
The technical field is computer modeling that tests microprocessor or chip design and function.
BACKGROUND
Current computer architectural testing often involves comparing the results of instructions executed on a reference model and instructions executed on a behavioral model. A microcode based machine is one in which a user visible instruction (macroinstruction) is broken down into a sequence of microinstructions that emulate the behavior of the macroinstruction, and are not directly visible to the user. On a microcode based machine, such testing is completed without microinstruction modeling or checking. Because current systems do not include modeling on the microinstruction level, current systems are only capable of checking the behavioral model on the macroinstruction boundaries in the emulated instruction set, or on transitions between the microinstruction set and native mode instruction set. In addition, current systems have not been able to verify the correctness of the microinstruction sequence and control (aliasing) information. Furthermore, current microcode simulators can only execute microinstructions without faults or traps, or other dynamic information. These simulators were designed for performance analysis rather than checking correctness.
SUMMARY
A method and apparatus for verifying the fine-granularity correctness of a behavioral model of a microcode machine central processing unit (CPU) that supports two instruction set architectures, where applications written for either instruction set architecture may be executed on the CPU. In computer systems, granularity may refer to how finely instructions executing on the CPU may be tested. That is, a fine granularity test may involve observing and recording the result of each specific action that the CPU completes in performing a function. Verifying a CPU on a finer granularity allows the designer to detect and isolate errors in the design more quickly. Additionally, finer-grained checking can detect incorrect behavior that may not be available with coarse-grained checking.
The two instruction set architectures may use a native mode instruction set and an emulated mode instruction set. In order to preserve compatibility with software applications that have been written to use the emulated instruction set without requiring the user to convert the software to the native mode instruction set, the designer causes the CPU to switch between the native mode instruction set and the emulated mode instruction set. Instructions in an emulated mode instruction set (or macroinstructions) are broken into a series of operations comprising instructions in a native instruction set (microinstructions, or microcode). The sequence of microcode is then executed, and the behavior of the CPU is reported and checked for correctness after each microinstruction is processed.
In order to verify the fine-grained correctness of a microcode based machine, the designer must be able to generate the sequence of microinstructions (microcode) needed to emulate the macroinstruction. The sequence of microcode for a given macroinstruction depends on dynamic execution information, and generally can not be statically predicted.
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Brockmann Russell C.
Brummel Karl P.
Knebel Patrick
Long Bruce A.
Petsinger Jeremy
Beausoliel Robert
Duncan Marc
Hewlett--Packard Development Company, L.P.
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