Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2000-02-04
2004-04-27
Wiley, David (Department: 2143)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S239000
Reexamination Certificate
active
06728872
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing systems and in particular to a method and apparatus for checking the sequencing of fetched instructions within a data processing system. Still more particularly, the present invention relates to a method and apparatus for enabling correct architectural sequencing of instructions placed within a processor pipeline.
2. Description of the Related Art
A conventional processor may include an instruction fetch unit (IFU) for requesting instructions to be loaded, an instruction cache for storing instructions, an instruction Buffer for temporarily storing instructions fetched from the instruction cache for execution, a number of execution units for executing sequential instructions, a branch processing unit (BPU) for executing branch instructions, a dispatch unit for dispatching sequential instructions from the instruction Buffer to particular execution units, and a completion Buffer for temporarily storing instructions that have finished execution, but have not been completed.
In these conventional processors, branch instructions and sequential instructions are handled differently. Address resolution, or the process of ensuring that an address is correct or matches the associated instruction is typically performed for branch instructions by the BPU. The BPU compares the supplied target addresses and branch direction for branch instructions with the computed architectural next address. All other instructions (e.g., inline instructions) are assumed to follow the correct architectural sequence when placed in the processor pipeline. When this assumption proves to be incorrect (i.e., instructions fall out of sequence) as occurs during unobserved data dependencies, hardware defects, crossing of information in cache lines, synchronous exceptions and instruction mis-sequencing, etc., in the processor not being able to continue its regular processing of instructions (referred to as a pipeline break—no useful information being processed by the processor), which ultimately leads to reduced processor efficiency.
The present invention thus recognizes that it would be desirable and beneficial to have a system or apparatus for ensuring that all instructions fetched by a processor into its pipeline follows the correct architectural sequencing. A system which supports instruction address resolution to provide all instructions in their correct sequence would be a welcomed improvement. Finally, the present invention recognizes that such a system would be further enhanced by providing efficient restart of instruction sequencing when an incorrectly sequenced instruction is located and removed from the pipeline.
These and other benefits are presented in the invention described herein.
SUMMARY OF THE INVENTION
A method and apparatus are disclosed for enabling the correct architectural sequencing of fetched instructions prior to allowing the instructions to complete in the processor pipeline to reduce the occurrence of pipeline breaks. A branch processing unit (BPU) is designed to perform sequence checks for the addresses of all instructions fetched into the pipeline (i.e., both in-line and branch instructions) by the instruction fetch unit (IFU). A first instruction is fetched. The address of the next instruction in the architectural sequence is computed and stored within the BPU. The next instruction is fetched and its address is compared to the next instruction address stored in BPU to determine if it is the correct address. If the next instruction address matches that of the architectural sequence, the instruction is permitted to “live” (i.e., continue through to completion). When the address does not match, the instruction is killed (i.e., not allowed to complete) and a new instruction is fetched by the IFU.
In a preferred embodiment, instructions can be killed at any stage of the pipeline. When an instruction is killed, its live signal is de-asserted, and travels through the remainder of the pipeline as though it was a none operation (nop) that does not advance the program counter. A register within the branch unit holds the architectural sequence address. If a live instruction from an incorrect address attempts to pass through the BPU, the BPU kills the instruction. When such an instruction is killed, the architecturally correct instruction address is loaded into the IFU to permit the IFU to continue fetching instructions from the point at which the last correct instruction was fetched. Thus, an almost instantaneous restart of instruction fetching is provided, which substantially reduces the occurrence of pipeline breaks at later pipeline stages.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4991080 (1991-02-01), Emma et al.
patent: 5222240 (1993-06-01), Patel
patent: 5542109 (1996-07-01), Blomgren et al.
patent: 5799167 (1998-08-01), Lesartre
patent: 5954814 (1999-09-01), Zaidi et al.
patent: 6189092 (2001-02-01), Ogura et al.
patent: 6279100 (2001-08-01), Tremblay et al.
patent: 0889395 (2001-09-01), None
patent: PUPA 98-83442 (1998-12-01), None
Flacks Brian King
Hofstee Harm Peter
Bracewell & Patterson L.L.P.
Collins Scott M.
Salys Casimer K.
Wiley David
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