Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-04-26
2003-06-17
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06581173
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of data integrity in a memory, and more particularly, to the field of verification of the integrity of memory contents.
2. Discussion of Related Art
It is important for reliable system operation to ensure that data stored in a memory is not corrupted.
There are several different events that have the potential to cause memory corruption. Some computer systems, for example, may provide the capability to enter a suspended state either on command, or following a timeout period. During the suspended state, only certain parts of the system are powered.
It is important to provide continuous and sufficient power to volatile memories in the system in order for the memories to reliably maintain the information stored therein. If the power to a memory or a cell within the memory is interrupted or insufficient during the suspended state, some of the data stored in the memory may be corrupted.
Systems that include the capability to enter a suspended or low power mode typically include software that is executed by a processor prior to the system entering the suspended state to preserve the context of the computer system. Along with saving the context of the system, the software may also include a routine that provides a signature or other indicator of the information stored in main memory at that time.
The signature or indicator may be a checksum or a cyclic redundancy checking (CRC) code, for example. The checksum or CRC code is generated based on data read from predetermined memory cells in the memory to be verified.
Upon exiting the suspended state, once the processor is reset, the processor reads data from the same memory locations and executes the same routine to provide a second signature or indicator of the information stored in the main memory. The second, post-suspend signature is compared to the first, pre-suspend signature to determine whether the information stored in the main memory was corrupted during the suspended state.
A disadvantage of this approach is that the integrity of the main memory cannot be verified until the processor is completely reset. This can cause a delay in resuming system operation after exiting the suspended state.
Another disadvantage of this approach in a computer system is that the processor cannot execute code from the main memory until the verification process is complete. The basic input/output system (BIOS) routine, for example, may be executed from electrically programmable read-only memory (EPROM) instead of the main memory. The datapath from the processor to the EPROM is often narrower than the datapath from the processor to the main memory thereby slowing down execution of the BIOS routine.
A further disadvantage of this approach is that the processing overhead involved in executing the software memory verification routine may unnecessarily slow down the memory verification process.
SUMMARY OF THE INVENTION
A method and apparatus for verifying that data stored in a memory has not been corrupted are described.
For one embodiment, an integrated circuit device includes dedicated memory verification logic to compare data read from a set of cells in a memory at a first time to data read from the same set of memory cells at a second time.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Chase Shelly A
Faatz Cynthia T.
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