Method and apparatus for verifying system-on-chip model

Details Method and apparatus for verifying system-on-chip model Method and apparatus for verifying system-on-chip model

2007-12-27

2009-10-20

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S001000

Reexamination Certificate

active

07607116

ABSTRACT:
A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification method includes acquiring first request information and first response information; acquiring second request information and second response information; dividing the first and second request information and the first and second response information; comparing the divided first and second request information and comparing the divided first and second response information; and verifying a modeling result on the TL model depending on the comparison results.

REFERENCES:
patent: 2006/0282233 (2006-12-01), Pasricha et al.
patent: 2008/0263486 (2008-10-01), Alexanian et al.

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