Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-02-07
2004-03-16
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06708323
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods and apparatuses for verifying mask pattern data of designed circuits according to given rules, the pattern data including a plurality of feature data.
2. Description of the Related Art
FIG. 9
is a schematic block diagram showing a prior art apparatus for verifying pattern data of a designed semiconductor integrated circuit.
A verification apparatus
10
is a computer on which a verification program is installed, to which an input device
11
, a display device
12
, and a storage device
13
are connected to constitute a computer system.
FIG. 10
is a flow chart showing processing associated with the apparatus of FIG.
9
.
(S
1
) Pattern data is designed and stored in the storage device
13
.
FIG. 11
shows hierarchical pattern data for example and the data includes a plurality of feature data.
(S
2
) The verification apparatus
10
reads the design data from the storage device
13
, flatten the data with loosing hierarchical structure, and verifies the design data according to given rules including design rules. If the verification apparatus
10
finds any feature data not meeting the rules, it causes the display device
12
to display the contents of the error. In order not to miss any error, the verification apparatus
10
detects all errors not meeting the rules. However, some of the errors may not problematical (false errors) in view of characteristics of a semiconductor integrated circuit. Accordingly, errors will be detected excessively.
(S
3
and S
4
) If no error is detected, then a designer writes such contents in a request form that a mask should be manufactured according to the design data stored in the storage device
13
, or else the process goes to step S
5
.
(S
5
) If any error exists but each error is judged by the designer to be false, then the process goes to step S
6
, or else the process returns to step S
1
to perform engineering change so that no true error is detected.
(S
6
) The same processing as in step S
4
is performed.
(S
7
) The designer additionally writes in the request form to notify that each detected error is false. In a mask manufacturing section, a processing shown in
FIG. 12
is performed with using another apparatus not shown.
(S
10
) Design data is read into the computer of this apparatus.
(S
11
) In order to manufacture a mask on which a desired pattern is formed, geometric processing associated with a pattern exposure system is performed. The geometric processing includes fracturing features of a pattern into basic features such as rectangles and triangles, reversal, scaling, sizing, rotation, mirror inversion, and geometric logic operation between layers.
Next, processed features are verified according to given rules. For example, it is checked whether or not there is a wrong feature such as a logically unexistable feature (an absurd feature). Although the verification has been basically performed in step S
2
of
FIG. 10
, new errors can arise after the above described geometric processing.
(S
12
) If the verification is finished without detecting any error, then the process goes to step S
14
, or else the process goes to step S
13
.
(S
13
) An operator checks the contents of the detected error whether or not it is a false one which has been written in the request form in step S
7
of
FIG. 10
, and if it is affirmative, then the process returns to step S
11
to continue for the rest features, or else he causes the computer to terminate the process and inquires the designer who wrote in the request form whether or not the error is problematic in view of characteristics of the semiconductor integrated circuit. In the inquiry, if it is found that the error is not problematic, then the process returns to step S
11
, or else the process returns to step S
1
of FIG.
10
.
(S
14
) The verified data are converted into a data format for the exposure system.
However, since human judgment intervenes in step S
13
, a suspended time becomes longer if the designer in charge is not available, for example, in a late night or on his holiday. Furthermore, the probability of human mistakes increases since the judgments in steps S
5
and S
13
are performed by different persons.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method and an apparatuses for verifying mask pattern data, capable of not only reducing a pattern data preparing time for manufacturing a mask but also decreasing human mistakes arising in the pattern data preparation.
In one aspect of the present invention, there is provided a computer implemented method for verifying pattern data of a designed circuit according to first given rules, the pattern data including a plurality of feature data, the method comprising the steps of:
in a design section,
(a) if there is any feature data not meeting the first given rules, outputting contents of this feature data as an error; and
(b) if first error information indicating that the error is not problematical in view of characteristics of the circuit is inputted, adding the first error information to a file including the pattern data;
in a mask manufacturing section,
(c) reading said file;
(d) processing for obtaining exposure data for manufacturing a mask, on feature data included in said file;
(e) verifying said feature data processed, according to second given rules; (f) if any feature data not meeting said second given rules exists, judging whether or not contents of this feature data is included in said first error information; and
(g) if judged to be included in step (f), then if said first error information indicates not being problematic, judging that said feature data not meeting said second given rules is not problematic.
In step (e), some of the detected errors may not problematical (false errors) in view of characteristics of a semiconductor integrated circuit.
However, with the above configuration, since the false errors which may occur in the mask manufacturing section are in advance included in the first error information added in the design section, almost no necessity of human judgment occurs after preparation of the first error information, which makes it possible to prepare an exposure data for manufacturing a mask in a shorter time than in the prior art.
Further, due to this almost no necessity, a probability of human mistakes is reduced.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.
REFERENCES:
patent: 5225993 (1993-07-01), Iwatsuki et al.
patent: 6063132 (2000-05-01), DeCamp et al.
patent: 6077310 (2000-06-01), Yamamoto et al.
patent: 6078737 (2000-06-01), Suzuki
patent: 6425112 (2002-07-01), Bula et al.
patent: 6-259503 (1994-09-01), None
patent: 07319933 (1995-12-01), None
Horie Tsutomu
Ohta Kazutoshi
Fujitsu Limited
Rossoshek Helen
Siek Vuthe
Staas & Halsey , LLP
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