Method and apparatus for verifying logic circuit

Details Method and apparatus for verifying logic circuit Method and apparatus for verifying logic circuit

2011-03-22

2011-03-22

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S108000, C716S111000, C716S136000, C703S013000, C703S014000

Reexamination Certificate

active

07913207

ABSTRACT:
A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.

REFERENCES:
patent: 5388215 (1995-02-01), Baker et al.
patent: 5687094 (1997-11-01), Kagawa et al.
patent: 6671846 (2003-12-01), Schultz
patent: 6675310 (2004-01-01), Bloom et al.
patent: 6802046 (2004-10-01), Coelho et al.
patent: 6915249 (2005-07-01), Sato et al.
patent: 2002/0049576 (2002-04-01), Meyer
patent: 2003/0208734 (2003-11-01), Coelho et al.
patent: 2005/0149312 (2005-07-01), McGaughy
patent: 2005/0268265 (2005-12-01), Ly et al.
patent: 2006/0271345 (2006-11-01), Kasuya
patent: 2007/0299647 (2007-12-01), Bolcato et al.
patent: 2008/0027699 (2008-01-01), Wu et al.
patent: 2008/0134115 (2008-06-01), Ly et al.
patent: 2008/0216032 (2008-09-01), McElvain et al.
patent: 10-0185796 (1999-05-01), None
patent: 1020050002497 (2005-01-01), None

Affiliated with

Also associated with

Rating

Method and apparatus for verifying logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for verifying logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for verifying logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2743633