Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2007-12-21
2011-10-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S106000, C714S724000, C714S739000, C714S741000
Reexamination Certificate
active
08042086
ABSTRACT:
A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction sequences that preserve instruction order dependencies and randomly selecting data values from a valid range of data values. Multiple instruction streamers may be employed to simulate interrupt handlers and other functional design units sharing a control command bus. A priority scheduler sequences the instruction sequences generated by multiple instruction streamers based on a specified priority scheme.
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Oracle America Inc.
Polsinelli Shughart PC
Siek Vuthe
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