Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-01-27
2001-04-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06216253
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a method and apparatus for verifying an electrical configuration, and more particularly to a method and apparatus for judging whether output terminals of a mask pattern and a circuit diagram correspond.
DESCRIPTION OF THE RELATED ART
Integrated circuits are produced by using mask patterns of the integrated circuits, based on circuit diagrams. For generating the mask patterns, verification is required as to whether the circuit diagrams and the circuit connections of the mask patterns are equivalent to each other. For this verification, computers are employed (e.g., a Computer Aided Design (CAD) computer system).
FIG. 1
is a flowchart showing a conventional method of verifying the coincidence between the circuit diagram and the mask pattern. In describing the verification method of
FIG. 1
,
FIGS. 2 and 3
are referred to for easy understanding of FIG.
1
.
FIG. 2
is an example of a circuit diagram containing a plurality of functional blocks (
100
-n (where n is a positive integer)). A functional block
100
has an input terminal
1
, an inverter
2
, a node
27
, and output terminals
3
,
4
. A functional block
101
has an input terminal
1
′, a buffer
2
′, and an output terminal
3
′.
FIG. 3
is an example of a mask pattern based on node
27
, and output terminals
3
,
4
in
FIG. 2
in which output terminals
9
,
13
are connected by contacts
8
,
11
, respectively, by using a first metal wire
6
.
Turning to the conventional method, first a circuit diagram such as that shown in
FIG. 2
is generated (step S
12
). Next, a mask pattern such as that shown in
FIG. 3
is designed based on the circuit diagram (step S
13
). In parallel with these procedures, output terminals (e.g., output terminals
3
,
4
, and
3
′) are extracted from the circuit diagram generated in step S
12
(step S
14
). Next, output terminals judged to have an equal electric potential (e.g., terminals
3
,
4
in
FIG. 2
) in step S
14
, are extracted (step S
15
).
Any one of the equal-potential output terminals is retained, but other terminals of the equal-potential output terminals are removed. This procedure is called “shrinkage”. Therefore, either terminal
3
or terminal
4
is removed (step S
16
) since these terminals are equal potential output terminals. The shrinkage is needed so that the CAD device can recognize that every equal-potential output terminal is identical. For example, the CAD device cannot distinguish terminal
3
from terminal
4
because they have the same potential. Therefore, any one output terminal of the equal-potential output terminals is selected as a representative by the CAD device although there are many output terminals having equal-potential.
Next, circuit connection information (e.g., the information that output terminal
3
′ is connected to input terminal
1
) is extracted from the circuit diagram (step S
17
).
In step S
18
, the information of the mask pattern designed in step S
13
is compared and collated with the circuit connection information extracted in step S
17
. At this time, the mask pattern as shown in
FIG. 3
, has a plurality of equal-potential output terminals
9
(OUT
1
) and
13
(OUT
2
) which have a different terminal name (designation), whereas the circuit connection information has only either one of output terminal
3
(OUT
1
) or output terminal
4
(OUT
2
) of FIG.
2
. Therefore, the CAD device detects an error (step S
19
).
When an error is detected in step S
19
, it is judged by the CAD device whether the error is a false error caused by a shrinkage in step S
16
or whether the error is a true error of mismatch caused by design mistakes (step S
20
). If a true error (e.g., a “NO” in step S
20
) exists, the method returns to step S
13
, and the mask pattern is redesigned. If only a false error exists due to the shrinkage (e.g., a “YES” in step S
20
), the circuit diagram and the mask pattern are assumed to match, and the verification ends.
However, a problem arises in that, to judge the false error, the conventional method and CAD apparatus require many steps and much time. Thus, system efficiency is poor.
SUMMARY OF THE INVENTION
In view of the foregoing problems of the conventional method and apparatus, it is therefore an object of the present invention to provide an improved method for verifying an electrical configuration (e.g., an electrical circuit).
It is another object of the present invention to provide an improved apparatus for verifying an electrical configuration.
In a first aspect, an apparatus and method according to the present invention includes designing a mask pattern from a circuit diagram, extracting output terminals which have equal potential from the mask pattern, and inserting at least one first pseudo-element pattern between the output terminals.
With the unique and unobvious structure and method of the present invention, the CAD apparatus can recognize easily the difference between output terminals which have a same potential because a pseudo-element pattern is inserted between the output terminals. Therefore, the steps and time required for verifying the electrical configuration are decreased, as compared to the conventional method and apparatus.
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patent: 5436097 (1995-07-01), Norishima et al.
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patent: 5763143 (1998-06-01), Sakura
patent: 338852 (1991-02-01), None
patent: 03152542 (1991-06-01), None
patent: 04128974 (1992-04-01), None
Heeb et al “Approximate Time-Domain Models of Three-Dimensional Interconnects,” IEEE, pp. 201-205, Sep. 1990.*
Sakata, T. et al., “A Circuit Comparison System for Bipolar Linear LSI”, in Proceedings of the Design Automation Conference (DAC), vol. Conf. 22, pp. 429-434, 1985.
Razdan, R., “HCNC: High Capacity Netlist Compare”, in Proceedings of the Custom Integrated Circuits Conference, vol. Conf. 15, pp. 170601-170605, 1993.
European Search Report dated Mar. 17, 2000.
“Basic super LSI CAD”; pub. Dec. 25, 1983; pp. 1, 146-151.
McGinn & Gibb, PLL
NEC Corporation
Siek Vuthe
Smith Matthew
LandOfFree
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