Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1997-05-30
2001-08-07
Peikari, Behzad James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S222000, C365S201000, C714S721000, C714S718000, C711S105000
Reexamination Certificate
active
06272588
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to integrated electronic circuits, and more specifically to methods and devices for testing such circuits.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is disclosed an apparatus and a method of verifying and characterizing data retention in a DRAM using built-in test circuitry which substantially eliminates disadvantages of known DRAMs.
The apparatus includes a DRAM periodically requiring a refresh operation to retain valid data, refresh control circuitry, and built-in test circuitry. The refresh circuitry initiates a refresh operation to satisfy a data retention time specification for the DRAM. The built-in test circuitry modifies a rate at which the refresh control circuitry performs the refresh operation in order to verify the actual data retention time of the DRAM. The method includes the steps of operating a DRAM to selectively modify a rate at which the refresh control circuitry performs the refresh operation.
BACKGROUND OF THE INVENTION
A common and well known test methodology for integrated circuits is Built-In Test (BIT) or Built-In-Self Test (BIST) which uses a dedicated portion of the integrated circuit to determine if the integrated circuit is free of manufacturing defects. BIST circuitry often generates stimulus for the circuitry under test. The tested circuitry generates responses to be compared by the BIST circuitry with expected responses. A result of the comparison is provided by the BIST circuitry for use by a manufacturer or user of the integrated circuit.
One particularly well-suited application of BIST is with memories due to the repetitive structures often found in memories. Dynamic Random Access Memories (DRAMs) have most of the same test requirements as Static Random Access Memories (SRAMs) but with an additional requirement of testing the data retention time specification. DRAMs are specified to have a maximum interval over which all rows must be refreshed. In particular, DRAMs have a characteristic that all read operations and all write operations have the effect of refreshing the row which is accessed. For normal system operation, this characteristic ensures that data is not destroyed by these accesses, but in no manner does it lessen the need to maintain the schedule of regular refreshing due to the random nature of the accesses in normal system operation. A production test of a DRAM must verify that refresh operations which are provided at the minimum specified rate are sufficient to ensure that the DRAM reliably retains all the data which has been stored.
Previous BIST architectures have generated a test sequence for testing memories. In one example, the test sequence is stored in ROM and therefore is programmable. An example of such a test architecture is disclosed in U.S. Pat. No. 5,173,906 entitled “Built-In Self Test for Integrated Circuits”. Another programmable test architecture is taught in U.S. Pat. No. 5,224,101 entitled “Micro-Coded Built-In Self Test Apparatus for a Memory Array”. Microcode is used to provide a delay period for data retention determined by a program stored in a Microcode ROM. However, this delay interval is subject to the clock frequency of the Built-In Test circuitry and is implemented as a counter clocked at a sequencer's clock rate.
If the test method provided for an embedded DRAM is Built-In-Self-Test (BIST), there is a problem that BIST circuitry is generally a finite state machine (FSM) which is designed to execute a predetermined sequence of states to stimulate the memory and evaluate the responses of the memory. State transitions in the predetermined BIST sequence are generally synchronous with one or more clock inputs. This clocking source is generally the same as is used for other circuitry with which the embedded DRAM is integrated. Thus, if a predetermined BIST sequence includes a refresh interval test, then the duration of the refresh interval which is produced by the BIST FSM will be directly related to the frequency of the BIST clocking source, whereas the function which must be guaranteed by the test is a specified data retention interval unrelated to the BIST clocking frequency.
Other circuitry with which the embedded DRAM is integrated (e.g. data processor circuitry) is generally designed and specified to operate reliably over a range of clock frequencies. If the BIST is to operate over the same range of frequencies as the other circuitry with which the embedded DRAM is integrated, there exists a problem of the BIST data retention interval being dependent on the clock frequency, particularly when a maximum data retention interval is being tested. Frequency dependency results in difficulty in applying a data retention interval test for a specific duration.
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Atwell William Daune
Giles Grady Lawrence
Johnston Thomas Kevin
Chastain Lee E.
King Robert L.
Motorola Inc.
Peikari Behzad James
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