Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-25
2005-01-25
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06848084
ABSTRACT:
This invention relates to method and apparatus for verification of circuit designs containing memories. At a register transfer abstraction level, verification of a circuit design requires showing that the register transfer language (RTL) abstraction of the design is logically equivalent to the design implementation represented at the logic (e.g., gate and/or flip-flop) and/or the transistor (e.g. implementation verification) abstraction levels, as well as logic simulation of the design RTL embedded in a system-level test bench for verification at the system-abstraction level.
REFERENCES:
patent: 5377122 (1994-12-01), Werner et al.
patent: 5493508 (1996-02-01), Dangelo et al.
patent: 5553002 (1996-09-01), Dangelo et al.
patent: 6026226 (2000-02-01), Heile et al.
patent: 6052524 (2000-04-01), Pauna
patent: 6053947 (2000-04-01), Parson
patent: 6053948 (2000-04-01), Vaidyanathan et al.
patent: 6249901 (2001-06-01), Yuan et al.
patent: 6295627 (2001-09-01), Gowni et al.
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6360356 (2002-03-01), Eng
patent: 6446243 (2002-09-01), Huang et al.
patent: 6470478 (2002-10-01), Bargh et al.
patent: 6490717 (2002-12-01), Pedersen et al.
patent: 6505328 (2003-01-01), Van Ginneken et al.
patent: 6601024 (2003-07-01), Chonnad et al.
patent: 20030005418 (2003-01-01), Sridhar et al.
patent: 20030107595 (2003-06-01), Ciolfi
Ludden, J.M. et al., “Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems”,IBM J. Res.&Dev.,vol. 46, No. 1, Jan. 2002, pp. 53-76.
Malley, Charles H. et al., “Logic Verification Methodology for PowerPC™ Microprocessors”.32ndDesign Automation Conference, ACM/IEEE, 1995, pp. 234-240.
Weste, Neil H.E., Principles of CMOS VLSI Design A Systems Perspective, 2nded.,Addison-Wesley Publishing Company, Oct. 1994.
Hines Mitchell W.
Lin Chih-Chang
Pandey Manish
Bingham & McCutchen LLP
Cadence Design Systems Inc.
Dimyan Magid Y.
Garbowski Leigh M.
LandOfFree
Method and apparatus for verification of memories at... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for verification of memories at..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for verification of memories at... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3396346