Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2002-01-03
2004-03-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S096000, C365S210130
Reexamination Certificate
active
06704236
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
[Not Applicable]
FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[Not Applicable]
SEQUANCE LISTING
[Not Applicable]
BACKGROUND OF THE INVENTION
One embodiment of the present invention relates to a memory device with a gated fuse element. More specifically, one embodiment of the present invention relates to verifying the state of a gated fuse element used with a one-time programmable CMOS memory device.
There are two main types of memory devices used in the field of data storage. The first type is volatile memory that has the information stored in a particular memory device, where the information is lost the instant power is removed. The second type is a non-volatile memory device in which the information is preserved even with the power removed. Of the second type, some designs provide for multiple programming while other designs provide for one-time programming. Typically, the manufacturing techniques used to form such non-volatile memories are quite different from standard logic processes, thereby dramatically increasing the complexity and chip size of such memories.
One-time programmable (alternatively referred to as “OTP”) memory devices have numerous applications, specifically long-term applications. For example, OTP memory devices may be used in post package programming to store security codes, keys or identifiers. These codes, keys or identifiers cannot be electrically altered or decoded without destroying the circuitry. Further, such OTP memory devices may be used to make a device unique for a specific application. Alternatively, such memory devices may be used as memory elements in programmable logic and read only memory devices.
Known OTP memory devices use storage elements combined with poly fuses. One disadvantage of poly fuses is that the resistance ratio is fairly close together, having only about one order of magnitude difference in value. In other words, the resistance of poly fuses before they are blown and the resistance after they are blown is fairly close. Therefore, sensing the difference between a blown and un-blown poly fuse is difficult. Yet another disadvantage of conventional poly fuses is the instability of their programmed state resistance. Specifically, the resistance of the programmed poly fuses tends to decrease over time. In the worst case, the programmed poly fuse may actually switch from the programmed state to the unprogrammed state resulting in circuit failure.
Thick oxide gated transistors or fuses (i.e., fuses fabricated according to 0.35 &mgr;m, 0.28 &mgr;m or other thick process technologies) have been used in place of poly fuse memory devices. U.S. Pat. No. 6,044,012 discloses a technique for rupturing the gate oxide transistor, where the oxide is about 40 to 70 Å thick. It is contemplated that the voltage required to rupture this thick oxide is substantially high and requires using a charge pump circuit. Furthermore, it is believed that the final programmed resistance is in the high kilo ohms range.
One alternative is to use an OTP CMOS memory device having thin-gated oxide transistors or fuses. Commonly assigned application Ser. No. 09/739,752, the complete subject matter of which is incorporated herein by reference, discloses the physical current used to rupture, breakdown or blow a gate-ox fuse, where the oxide is about 2.5 nm thick or less (alternatively referred to as “thin oxide” or “thin gate-ox transistor or fuse”). These thin gate-ox transistors or fuses integrate both NMOS and PMOS transistors on a silicon substrate. The NMOS transistor consists of a N-type doped polysilicon gate, a channel conduction region, and source/drain regions formed by diffusion of N-type dopant in the silicon substrate. The channel region separates the source from the drain in the lateral direction, whereas a layer of dielectric material that prevents electrical current flow separates the polysilicon gate from the channel. Similarly, the PMOS transistor architecture is the same as the NMOS transistor provided previously but using a P-type dopant.
The dielectric material separating the polysilicon gate from the channel region usually consists of thermally grown oxide material, silicon dioxide (SiO
2
) for example, where the oxide is about 2.5 nm thick or less. Here the thin oxide leaks very little current, through a mechanism called Fowler-Nordheim tunneling, under voltage stress. When this thin gate-ox transistor or fuse is stressed beyond a critical electrical field (applied voltage divided by the thickness of the oxide) the oxide ruptures, destroying (alternatively referred to as “blowing”) the transistor or fuse. If the fuse is connected or coupled to a storage element as part of a memory cell as disclosed in commonly assigned application Ser. No. 10/025,132 now U.S. Pat. No. 6,525,955, titled “Memory Cell with Fuse Element”, the complete subject matter of which is incorporated herein by reference, blowing the transistor or fuse sets the state or programs the storage element and thus the memory cell.
Setting the state or programming the memory device effectively changes the parameters thereof. More specifically, setting the state of the transistor or fuse is a destructive act, as the blown fuse is effectively destroyed. After programming a memory device, it is advantageous to verify such programming. In other words, once the state of the fuse is set, it is advantageous to verify that such set state is correct and will not vary over the life time of the memory cell.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
Features of the present invention may be found in a one-time programmable CMOS memory device and method of verifying the programmed state of a gate-ox fuse used in a one-time programmable CMOS memory device. In one embodiment, the memory cell or device comprises comparing the resistance of a programmed fuse to a reference level, which is determined from experimental measurements from reference fuses.
One embodiment of the present invention relates to a method of verifying a state of an element having at least two states. The method comprises determining if the state of the element is equal to an expected state using a verify circuit and outputting a valid signal if the state of the element is equal to the expected state.
Yet another embodiment relates to a method for verifying a state of a memory device. The method comprises comparing a state of a first gated fuse to a first expected state and generating a first signal. A state of a second gated fuse is compared to a second expected state and a second signal is generated. A valid signal is output if both the first and second signals are the same.
One embodiment of the present invention relates to a method for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.
In another embodiment, the present invention relates to a verify device. In this embodiment, the verifying device comprising at least one current amplifier qualified by a data input.
In yet another embodiment, the present invention relates to a memory device. The memory device comprises at least one memory cell having at least one gated fuse and at least one reference cell. At least one verify circuit co
Buer Myron J.
Smith Douglas D.
Broadcom Corporation
Elms Richard
Hur J. H.
McAndrews Held & Malloy Ltd.
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