Pulse or digital communications – Synchronizers
Reexamination Certificate
1998-11-25
2001-09-04
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
C327S165000
Reexamination Certificate
active
06285722
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to recovering timing clock of signals in communication networks, and more particularly, to methods and apparatuses for recovering timing clock of variable bit rate signals in communication networks.
2. Background of the Art
High reliability networks, which handle diverse types of traffic from diverse sources, monitor and manage in the time domain the quality of digital transmission. Failure to detect and correct transmission impairments results in unacceptable link error rates and unexpected network failures. Hence, networks must extract from a stream of transmitted data a clock signal to perform the necessary measurements and correct for inevitable transmission degradation.
An extracted clock signal is necessary to perform time domain measurements, such as eye-pattern opening and timing jitter. The extracted clock signal is also essential for distinguishing the individual data bits in the transmitted data stream prior to further processing, such as digital demultiplexing, protocol conversion, packet switching, and measurement of bit error rate (BER).
Clock recovery has traditionally been regarded as a rate specific process, and as a result, conventional point-to-point transmission systems typically use only one or two line rates. Emerging network technologies, for example photonic switching and Wavelength Division Multiplexing (WDM), however, have enabled complex optical network topologies, where links transport diverse types of traffic, such as Internet Protocol (IP), Asynchronous Transfer Mode (ATM), Fiberchannel, Synchronous Optical Network (SONET), and Gigabit Ethernet. Hence, these emerging networks must use clock recovery circuits that are adaptive to the variable rate of the transmitted data.
A phase locked loop is one type of tracking filter often used in a clock recovery circuit for extracting a clock signal from an input data signal.
FIG. 1
illustrates the primary components of a prior art clock recovery circuit
100
, which includes a phase locked loop. The phase locked loop includes a phase comparator
120
, low pass filter
130
, a stable voltage controlled oscillator
150
(VCO), and feedback loop
165
.
As shown, a transition detector
110
, for example a dual edge triggered one-shot, receives a non-return to zero (NRZ) input signal
155
, and generates a single pulse of duration &tgr;
ED
for each transition in input signal
155
. The phase locked loop, whose passband frequency f
c
is centered on the bit rate frequency f
bit
of input signal
155
, extracts the clock signal from the stream of pulses generated by transition detector
110
. Phase comparator
120
compares the phase of the signal at the output of the phase locked loop with the stream of pulses, and generates a phase difference signal. Low pass filter
130
filters and amplifies the phase difference signal to generate a correction signal for adjusting the phase of VCO
150
.
For a variable bit rate NRZ input signal, two rate dependent parameters must be properly adjusted in clock recovery circuit
100
for recovering an associated clock signal
160
. One rate dependent parameter is the width &tgr;
ED
of the pulses generated by transition detector
110
. While input signal
155
generally does not contain energy at its bit rate frequency f
bit
, the series of pulses generated by transition detector
110
does contain energy at the bit rate frequency f
bit
. The amount of energy at the bit rate frequency f
bit
is maximum when the width of the generated pulses &tgr;
ED
equals 1/(2f
bit
).
The center frequency of VCO
150
is the second rate dependent parameter, which must be properly set to recover clock signal
160
from input signal
155
. An active or passive stabilization signal
170
initially sets the center frequency of VCO
150
to a value f
c
in the absence of a signal from phase comparator
120
. Feedback loop
165
causes the center frequency of VCO
150
to shift from the initial frequency f
c
to the bit rate frequency f
bit
of input signal
155
. VCO
150
will lock to the bit rate frequency f
bit
when its center frequency is close to the bit rate frequency f
bit
. When the center frequency of VCO
150
exactly equals the bit rate frequency f
bit
, VCO
150
will phase lock to transitions in input signal
155
.
In addition to a phase locked loop, clock recovery circuits may also include a frequency locked loop for tuning the center frequency f
c
of VCO
150
to the bit rate frequency f
bit
.
FIG. 2
illustrates the basic components of a clock recovery circuit
200
, which includes a transition detector
210
, phase comparator
220
, frequency comparator
260
, low pass filter
230
, and VCO
250
. Frequency comparator
220
compares the stream of pulses generated by transition detector
210
with the output of VCO
250
, and generates a locking signal that reflects the difference between the center frequency of VCO
250
and the bit rate frequency f
bit
. An adder
270
combines the locking signal with the output of phase comparator
220
. Feedback loop
265
causes the center frequency of VCO
250
to shift from its initial value of f
c
to the bit rate frequency f
bit
, causing the locking signal to transition to zero. At this point, phase comparator
120
continues to control the center frequency and phase of VCO
250
.
The stream of pulses generated by transition detector
210
also contains at multiples of the bit rate frequency f
bit
energy, whose relative amplitude increases as &tgr;
ED
decreases. As a result, regular patterns in block coded input signals may produce both harmonics and sub-harmonics of the bit rate frequency f
bit
. Accordingly, existing clock recovery circuits track the harmonics or sub-harmonics of the input data signal when the center frequency of VCO
250
is inappropriately set to a multiple of the bit rate frequency f
bit
. Consequently, false locking may occur when a clock recovery circuit searches for the bit rate frequency f
bit
by sweeping the center frequency of VCO
250
across the harmonics. In addition, recurrent patterns in common block coded input data signals also increase the susceptibility of a clock recovery circuit to sub-harmonic locking.
Although various techniques are known for sweeping the center frequency of VCO
250
to determine the bit rate frequency f
bit
, these techniques are too slow and/or lack sufficient accuracy for variable bit rate applications. One example of variable bit rate applications is Wavelength Division Multiplexing (WDM), where an input data signal can have a wide range of bit rates. In addition, the existing techniques cause a clock recovery circuit to readily lock to harmonics and sub-harmonics of the bit rate frequency f
bit
.
Thus, it is desirable to have methods and apparatuses that do not have the above-mentioned and other disadvantages of the prior art clock recovery circuits for recovering a clock signal from a variable bit rate input data signal.
DESCRIPTION OF THE INVENTION
Methods and apparatuses consistent with the present invention recover a clock signal of a variable bit rate data signal by estimating the minimum time interval between transitions in the data signal, and based on the estimated minimum time interval, determining a center frequency of a narrow band filter that extracts the clock signal from the data signal. For example, a clock recovery circuit consistent with the present invention extracts the clock signal from the variable bit rate data signal by estimating a minimum time interval between transitions in the data signal. The clock recovery circuit generates a plurality of pulses that correspond to transitions in the data signal, and adjusts the duration of each of the pulses based on the estimated minimum time interval. The clock recovery circuit inputs into a narrow band filter the adjusted pulses, determines a center frequency of the narrow band filter based on the estimated minimum time interval, and extracts in the narrow-band filter the clock signal from the adjusted pulses.
Banwell Thomas C.
Cheung Nim K.
Cockings Orville
Corrielus Jean
Giordano Joseph
Pham Chi
Telcordia Technologies Inc.
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