Static information storage and retrieval – Addressing – Multiplexing
Reexamination Certificate
2000-06-08
2001-08-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Multiplexing
C365S203000, C365S189020
Reexamination Certificate
active
06282140
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to integrated circuits in general, and in particular to multiplexors. Still more particularly, the present invention relates to a multiplexor having a single event upset immune data keeper circuit.
2. Description of the Prior Art
High-speed static random access memories (SRAMs) typically require a group of special sensing circuits, commonly known as sense amplifiers, to sense and amplify any small signal delivered by a storage cell that is selected for a read operation. While using six-transistor cells as storage cells for data storage, a single-port or multi-port SRAM also use a bitline pair to connect the storage cells to a respective column of sense amplifiers to provide differential sensing. The sense amplifiers are then coupled to a group of multiplexors that employs data keeper circuits for data output from any one of the columns.
Referring now to the drawings and in particular to
FIG. 1
, there is illustrated a schematic diagram of a multiplexor having a data keeper circuit according to the prior art. As shown, a multiplexor
10
includes a data keeper circuit
14
, a p-channel precharge transistor
15
, and a series of n-channel input transistors
16
a
-
16
n.
Data keeper circuit
14
includes a p-channel keeper transistor
11
and an inverter
12
. The drain of keeper transistor
11
is connected to the input of inverter
12
, and the gate of keeper transistor
11
is connected to the output of inverter
12
. Data keeper circuit
14
is also coupled to p-channel precharge transistor
15
and n-channel input transistors
16
a
-
16
n.
Inputs IN
0
through IN
n
are connected to a gate of a corresponding one of input transistors
16
a
-
16
n.
During a precharge cycle (i.e., when the clock signal to the gate of transistor
15
is low), a precharge node x is precharged to a logical high state. During an evaluation cycle (i.e., when the clock signal to the gate of transistor
15
is high), inputs IN
0
-IN
n
are evaluated and the result appears at the output of multiplexor
10
. When the clock signal to the gate of transistor
15
is low again for the next precharge cycle, a logical high state is maintained within data keeper circuit
14
.
In order to improve the speed of multiplexor
10
, the precharge cycle is often shortened such that the precharge cycle can be completed before the evaluation cycle begins. During this transition period, transistor
15
and input transistors
16
a
-
16
n
are all turned off, and thus, precharge node x is “floating.” As a result, precharge node x becomes very susceptible to single event upsets (SEUs) that may affect the data stored within data keeper circuit
14
. The present disclosure provides an improved multiplexor to handle this problem.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a multiplexor having a single event upset (SEU) immune data keeper circuit includes a precharge transistor, an isolation transistor, an invertor, and an SEU immune storage cell. Both the gate of the precharge transistor and the gate of the isolation transistor are connected to a clock signal. The SEU immune storage cell has a first access node and a second access node. The first access node is complementary to the second access node. The first access node is connected to the precharge transistor and the second access node is connected to the isolation transistor. The invertor is coupled between the precharge transistor and the isolation transistor.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5828610 (1998-10-01), Rogers et al.
patent: 5905684 (1999-05-01), Hill
Li Bin
Phan Ho Gia
Bracewell & Patterson L.L.P.
Lam David
Nelms David
Ng Antony P.
Systems Integration Inc.
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