Method and apparatus for validating prefetched instruction

Details Method and apparatus for validating prefetched instruction Method and apparatus for validating prefetched instruction

1986-10-07

1987-12-01

Williams, Jr., Archie E.

Boots, shoes, and leggings

371 16, G06F 1100, G06F 938

Patent

active

047108665

ABSTRACT:
A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.

REFERENCES:
patent: 4370710 (1983-01-01), Kroft
patent: 4476525 (1984-10-01), Ishii
patent: 4484308 (1984-11-01), Lewandowski et al.
patent: 4500959 (1985-02-01), Kubo et al.
patent: 4521851 (1985-06-01), Trubisky et al.

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