Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-11
2007-12-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10774857
ABSTRACT:
A method for designing a system includes determining minimum and maximum delay budgets for connections. Routing resources are selected for connections in response to the minimum and maximum delay budgets.
REFERENCES:
patent: 5237514 (1993-08-01), Curtin
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5649167 (1997-07-01), Chen et al.
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5764528 (1998-06-01), Nakamura
patent: 6286126 (2001-09-01), Raghavan et al.
patent: 6349402 (2002-02-01), Lin
patent: 6578183 (2003-06-01), Cheong et al.
patent: 6701505 (2004-03-01), Srinivasan
patent: 6701506 (2004-03-01), Srinivasan et al.
patent: 6708139 (2004-03-01), Rearick et al.
patent: 6763506 (2004-07-01), Betz et al.
patent: 6836753 (2004-12-01), Silve
patent: 6871336 (2005-03-01), Anderson
patent: 6973632 (2005-12-01), Brahme et al.
patent: 7062743 (2006-06-01), Kahng et al.
patent: 7076758 (2006-07-01), Srinivasan et al.
patent: 2001/0049814 (2001-12-01), Matsumoto et al.
patent: 2002/0073389 (2002-06-01), Elboim et al.
patent: 2003/0005398 (2003-01-01), Cho et al.
patent: 2003/0051222 (2003-03-01), Williams et al.
patent: 2003/0088842 (2003-05-01), Cirit
patent: 2004/0230921 (2004-11-01), Hathaway et al.
patent: 2004/0243964 (2004-12-01), McElvain et al.
patent: 2005/0039156 (2005-02-01), Catthoor et al.
patent: 2005/0132318 (2005-06-01), Kidd et al.
patent: 2005/0138578 (2005-06-01), Alpert et al.
patent: 2005/0251775 (2005-11-01), Wood
NN9107410, “Linear Algorithm for Distributing Slack So That All Nets of a Design Have a Zero Slack Pin”, IBM Technical Disclosure Bulletin, vol. 34, No. 2, Jul. 1991, pp. 410-414.
Mathur et al., “Timing-Driven Placement for Regular Architecures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 6, Jun. 1997, pp. 597-608.
Betz Vaughn
Chow William
Fung Ryan
Altera Corporation
Chiang Jack
Cho L.
Tat Binh
LandOfFree
Method and apparatus for utilizing long-path and short-path... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for utilizing long-path and short-path..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for utilizing long-path and short-path... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3836281