Method and apparatus for utilizing long-path and short-path...

Details Method and apparatus for utilizing long-path and short-path... Method and apparatus for utilizing long-path and short-path...

2007-04-17

2007-04-17

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10774883

ABSTRACT:
A method for designing a system includes generating minimum and maximum delay budgets for connections from long-path and short-path timing constraints. The system is designed in response to the minimum and maximum delay budgets.

REFERENCES:
patent: 5237514 (1993-08-01), Curtin
patent: 5475607 (1995-12-01), Apte et al.
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5987086 (1999-11-01), Raman et al.
patent: 6006024 (1999-12-01), Guruswamy et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6408427 (2002-06-01), Cong et al.
patent: 6453446 (2002-09-01), van Ginneken
patent: 6480991 (2002-11-01), Cho et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6591411 (2003-07-01), Alpert et al.
patent: 6708139 (2004-03-01), Rearick et al.
patent: 6763506 (2004-07-01), Betz et al.
patent: 6826733 (2004-11-01), Hathaway et al.
patent: 6836753 (2004-12-01), Silve
patent: 6904585 (2005-06-01), Brittain et al.
patent: 6996512 (2006-02-01), Alpert et al.
patent: 7000206 (2006-02-01), Kidd et al.
patent: 7003747 (2006-02-01), Zhou et al.
patent: 7003754 (2006-02-01), Teig et al.
patent: 7013450 (2006-03-01), Teig et al.
patent: 7073150 (2006-07-01), Teig et al.
patent: 7133819 (2006-11-01), Hutton
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2002/0116685 (2002-08-01), van Ginneken
patent: 2002/0133799 (2002-09-01), Alpert et al.
patent: 2002/0161947 (2002-10-01), Ikeda et al.
patent: 2003/0005398 (2003-01-01), Cho et al.
patent: 2003/0115566 (2003-06-01), Teig
patent: 2003/0149954 (2003-08-01), McElvain et al.
patent: 2004/0123261 (2004-06-01), Alpert et al.
patent: 2004/0243964 (2004-12-01), McElvain et al.
patent: 2005/0034091 (2005-02-01), Harn
patent: 2005/0039156 (2005-02-01), Catthoor et al.
patent: 2005/0050497 (2005-03-01), Tetelbaum
patent: 2005/0120319 (2005-06-01), van Ginneken
patent: 2005/0132318 (2005-06-01), Kidd et al.
patent: 2005/0138578 (2005-06-01), Alpert et al.
patent: 2005/0251775 (2005-11-01), Wood
patent: 2006/0048086 (2006-03-01), Pie et al.
patent: 2006/0150127 (2006-07-01), Zhou et al.
NN9107410, “Linear Algorithm for Distributing Slack So That All Nets of A Design Have a Zero Slack Pin”, IBM Technical Disclosure Bulletin, vol. 34, No. 2, Jul. 1991, pp. 410-414 (7 pages).
Mathur et al., “Timing-Driven Placement for Regular Architectures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 6, Jun. 1997, pp. 597-608.

Affiliated with

Also associated with

Rating

Method and apparatus for utilizing long-path and short-path... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for utilizing long-path and short-path..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for utilizing long-path and short-path... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3806636