Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
2001-03-22
2004-05-18
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C700S110000, C700S175000, C324S765010
Reexamination Certificate
active
06738731
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology and, more particularly, to a method and apparatus for using tool state information to identify faulty wafers.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Occasionally, during the fabrication process, one or more process steps are omitted on a production wafer. Such omissions may be due to an error in the fabrication facility automated work flow system (e.g., a database or control script error), a tool failure, or an operator error. If the omitted process steps occur early during the fabrication process, it is not uncommon for the faulty wafer to undergo many subsequent steps prior to the faulty fabrication being identified. Often such identification occurs much further down the processing line, such as during the performance of electrical tests on the devices formed on the wafer. As a result, many resources, such as materials, tool time, operator time, etc., are wasted until the faulty fabrication can be identified.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for identifying faulty wafers. The method includes processing a set of wafers in a tool; collecting tool state information during the processing of the set of wafers; generating a tool state information baseline; comparing the tool state information for each wafer to the tool state information baseline to identify any wafers with outlying tool state information; and designating a particular wafer in the set as suspect in response to identifying outlying tool state information for the particular wafer.
Another aspect of the present invention is seen in a processing line including a tool adapted to process a set of wafers, and a process controller. The process controller is adapted to collect tool state information during the processing of the set of wafers, generate a tool state information baseline, compare the tool state information for each wafer to the baseline tool state information to identify any wafers with outlying tool state information, and designate a particular wafer in the set as suspect in response to identifying outlying tool state information for the particular wafer.
REFERENCES:
patent: 6374150 (2002-04-01), Redinbo et al.
patent: 6442445 (2002-08-01), Bunkofske et al.
patent: 6465263 (2002-10-01), Coss, Jr. et al.
patent: 6535783 (2003-03-01), Miller et al.
Knox Kent F.
Riley Terrence J.
Scheid Glen W.
Wang Qingsu
Advanced Micro Devices , Inc.
Hoff Marc S.
Kim Paul L
Williams Morgan & Amerson P.C.
LandOfFree
Method and apparatus for using tool state information to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for using tool state information to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for using tool state information to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3207569