Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2001-03-22
2004-10-12
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S245000, C712S231000, C711S135000
Reexamination Certificate
active
06804770
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to data processing and, in particular, to hazard prediction in a microprocessor design. Still more particularly, the present invention provides a method and apparatus for using past history to avoid flush conditions in a microprocessor design.
2. Description of Related Art
Pipeline processing is a technique that provides simultaneous, or parallel, processing within a computer. It refers to overlapping operations by moving data or instructions into a conceptual pipe with all stages of the pipe processing simultaneously. For example, while one instruction is being executed, the computer may be decoding the next instruction. In vector processors, several steps in a floating point operation may be processed simultaneously.
The pipeline is divided into segments and each segment can execute its operation concurrently with the other segments. When a segment completes an operation, it passes the result to the next segment in the pipeline and fetches the next operation from the preceding segment. The final results of each instruction emerge at the end of the pipeline in rapid succession.
Out of order execution is a technique used to gain an edge in speed and performance. However, occasionally out of order execution may create a hazard. A hazard may cause the microprocessor to flush the fetched but incomplete instructions from the pipeline stages and to subsequently refill the pipe. However, as the number of pipeline stages in a processor increases, the overhead of flushing and refilling the pipe also increases. For long pipelines, it may be better to stall the pipe than to flush and restart it.
Therefore, it would be advantageous to provide a method and apparatus for using past history to avoid flush conditions in a microprocessor.
SUMMARY OF THE INVENTION
The present invention provides a hazard prediction array consisting of an array of saturating counters. The array is indexed through a portion of the instruction address. At issue, the hazard prediction array is referenced and a prediction is made as to whether the current instruction or group of instructions is likely to encounter a flush. If the prediction is that it will flush, the instruction is not issued until it is the next instruction to complete. If the prediction is that the instruction will not flush, it is issued as normal. At completion time, the prediction array is updated with the actual flush behavior. When an instruction is predicted to flush and, thus, not issued until it is the next to complete, the predictor may be updated as if the instruction did not flush.
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Logan Douglas Robert
Mericas Alexander Erik
Starke William John
International Business Machines - Corporation
McBurney Mark E.
Pan Daniel H.
Yee Duke W.
Yociss Lisa L. B.
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