Electrical computers and digital processing systems: support – Computer power control – Having power source monitoring
Reexamination Certificate
2000-07-20
2004-02-24
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Having power source monitoring
C713S300000
Reexamination Certificate
active
06697955
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to processing systems and specifically to a power factor correction circuit for a processing system.
BACKGROUND OF THE INVENTION
Power factor correction (PFC) circuits are commonly used in desktop computers where a high power factor is required.
FIG. 1
depicts a conventional PFC circuit configuration
10
. The PFC circuit configuration
10
includes a boost stage portion
11
coupled to an isolated DC/DC converter portion
12
. The boost stage portion
11
includes an AC line voltage input
13
coupled to a rectifier bridge
14
wherein the rectifier bridge
14
is coupled to a first capacitor
16
. The first capacitor
16
is coupled to an inductor
18
wherein the inductor
18
is coupled to a diode
22
and a transistor
24
. The transistor
24
is coupled to a pulse width modulator
20
and the diode
22
is coupled to a bulk capacitor
26
.
The isolated DC/DC converter portion
12
includes a transistor
28
coupled to a transformer
30
wherein the transformer
30
is coupled to a first diode
32
. The first diode
32
is coupled to a second diode
36
and an inductor
34
. The inductor
34
is coupled to an output
38
and a capacitor
40
. The boost stage
11
develops a high voltage (i.e. 400V) across the bulk capacitor
26
and the isolated DC/DC converter portion
12
converts the high voltage to a lower voltage (for example, 5V) output.
During computer operation, the interruption of the AC line voltage is a relatively common occurrence. Based on these interruptions, it is required that the PFC circuit be capable of providing a regulated output for at least 20 ms. Utilizing a conventional approach, the bulk capacitor
26
is designed to store enough energy to provide regulated outputs at full load for up to 20 ms in the case of an AC line voltage interruption. This requires the implementation of a large (470 micro farad or higher) and relatively expensive bulk capacitor
26
. Furthermore, the diodes
32
,
36
and the transistor
28
of the isolated DC/DC converter portion
12
must be selected to account for the use of the large bulk capacitor
26
. Consequently, the diodes
32
,
36
and the transistor
26
of the isolated DC/DC converter portion
12
are higher rated (i.e. more expensive) components.
Accordingly, what is needed is an improved PFC circuit that less expensive than conventional PFC circuits. The circuit should be simple, cost effective and capable of being easily adapted to current technology. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A power factor correction circuit is disclosed. The power factor correction circuit comprises a converter portion, a boost stage portion coupled to the converter portion, and an energy reserve portion coupled to the boost stage portion, the energy reserve portion for providing a voltage for the power factor correction circuit in the event of an interruption of power to the circuit.
Through the use of the circuit in accordance with the present invention, the use of expensive, higher rated circuitry components is avoided. By avoiding the use of expensive higher rated circuitry components a significant reduction in manufacturing costs is achieved.
REFERENCES:
patent: 5216284 (1993-06-01), Mattes et al.
patent: 5420790 (1995-05-01), Ravas et al.
patent: 6043705 (2000-03-01), Jiang
patent: 6222746 (2001-04-01), Kim
patent: 10295041 (1998-11-01), None
“Power Factor Correction Circuit”, IBM Technical Disclosure Bulletin, Mar. 1, 1996, US, pp. 43-46.
Hemena William
Malik Randhir S.
Lee Thomas
Sawyer Law Group
Yanchus, III Paul
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