Method and apparatus for using address traps to pace writes...

Details Method and apparatus for using address traps to pace writes... Method and apparatus for using address traps to pace writes...

2006-11-14

2006-11-14

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C710S060000, C710S260000, C713S401000, C712S244000

Reexamination Certificate

active

07136944

ABSTRACT:
A system and method for pacing writes to a legacy peripheral device includes a control block configured to trap on the address of the legacy peripheral device and slows the rate that the CPU posts writes to avoid backpressure.

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