Method and apparatus for use of a host address to validate acces

Details Method and apparatus for use of a host address to validate acces Method and apparatus for use of a host address to validate acces

1998-08-04

2000-08-01

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714 53, 714719, 714805, 714819, 711114, G11C 2900

Patent

active

060981903

ABSTRACT:
A memory system constructed in accordance with the invention receives data blocks and associated host LBAs from a host processor. The memory subsystem initially associates a check value with each received data block, each check value dependent upon a host LBA that is associated with the respectively received data block. The memory subsystem stores each received data block and associated check value as an "extended" data block. Thereafter, the memory subsystem, in response to a host processor request to access data corresponding to the associated host LBA, recovers the stored extended data block and determines from the check value stored therewith, if the address of the corresponding data and that provided by the host processor correspond. If the addresses correspond, the data block is transmitted to the host processor. If not, an error message is generated.

REFERENCES:
patent: 4637024 (1987-01-01), Dixon et al.
patent: 5301297 (1994-04-01), Menon et al.
patent: 5469453 (1995-11-01), Glider et al.
patent: 5504858 (1996-04-01), Ellis et al.
patent: 5774643 (1998-06-01), Lubbers et al.

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