Method and apparatus for upper level substrate isolation integra

Details Method and apparatus for upper level substrate isolation integra Method and apparatus for upper level substrate isolation integra

1997-07-11

2000-10-31

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438479, 257347, 257500, 257501, H01L 2100, H01L 2184, H01L 2701, H01L 2712

Patent

active

061401633

ABSTRACT:
A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.

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