Computer graphics processing and selective visual display system – Computer graphics display memory system – Memory allocation
Reexamination Certificate
2005-09-13
2005-09-13
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Memory allocation
C345S531000, C345S556000, C345S558000, C345S538000
Reexamination Certificate
active
06943800
ABSTRACT:
In a graphics processing circuit, up to N sets of state data are stored in a buffer such that a total length of the N sets of state data does not exceed the total length of the buffer. When a length of additional state data would exceed a length of available space in the buffer, storage of the additional set of state data in the buffer is delayed until at least M of the N sets of state data are no longer being used to process graphics primitives, wherein M is less than or equal to N. The buffer is preferably implemented as a ring buffer, thereby minimizing the impact of state data updates. To further prevent corruption of state data, additional sets of state data are prohibited from being added to the buffer if a maximum number of allowed states is already stored in the buffer.
REFERENCES:
patent: 6088044 (2000-07-01), Kwok et al.
patent: 6268874 (2001-07-01), Niu et al.
patent: 6525737 (2003-02-01), Duluk et al.
Mantor Michael J.
Taylor Ralph C.
ATI Technologies Inc.
Bella Matthew C.
Nguyen Hau
Vedder Price Kaufman & Kammholz P.C.
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