Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Patent
1998-06-26
2000-02-01
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
G06F 114
Patent
active
060215054
ABSTRACT:
The present invention is a method and apparatus for updating a timer from a plurality of timing domains. An arbitration circuit arbitrates the update requests from the plurality of timing domains. The plurality of timing domains include at least a counter. The update requests provide the update values. A multiplexer, which is coupled to receive the update values, selects a timer value from the update values. A timer register which is coupled to the multiplexer stores the timer value synchronously with a local clock signal.
REFERENCES:
patent: 5023771 (1991-06-01), Kishi
patent: 5138707 (1992-08-01), Haller et al.
patent: 5210748 (1993-05-01), Onishi et al.
patent: 5491815 (1996-02-01), Basso et al.
patent: 5671357 (1997-09-01), Humblet et al.
Ayyagari Bhuvaneshwari
Raman Rajesh
Heckler Thomas M.
Intel Corporation
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