Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-20
2003-04-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06546532
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to computer-aided design (CAD) techniques for placement of logic functions and cells on an integrated circuit chip during the chip design process. The invention is more specifically related to a method and apparatus, typically embodied in a CAD system, for selecting and aligning cells on an application specific integrated circuit (ASIC).
BACKGROUND OF THE INVENTION
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form.
Chip designers generally employ hierarchical design techniques to determine the appropriate selection and interconnection of logic and/or memory devices that will enable the chip to perform the desired function. These techniques involve describing the chip's functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
The hierarchy of a logic design typically has “N” levels of functions, where N is an integer (N>=1) representing the number of hierarchical levels of functionality in the chip. The first level is typically the chip itself. Each of the lower levels of hierarchy, such as when “N” is an integer (1<=n<=N), represent the level of any particular function in the hierarchy. A function consists of a discrete logic and/or memory element, or any combination of such elements. It may be as simple as an inverter or a flip-flop, having one or only a few transistors, or as complex as a shift register, an arithmetic logic unit (ALU), or even a microprocessor.
A parent function at the (N) level of the hierarchy is defined as a plurality of (N+1) level functions, each of which is a child function. For example, a microprocessor at the (N) level might be defined as the parent of the following (N+1) level children: an ALU, a series of registers, a bus, and various other functions (each of which may or may not have a plurality of (N+2) level children, and so on). Each child function which is not also a parent function (i.e., which has no children) is referred to as a leaf function or cell. Each leaf cell in a design is connected to at least one other leaf cell, such connection being commonly referred to as a “net.” The set of nets, each of which often defines a plurality of interconnected functions, is commonly referred to as a “netlist.”
It is useful to distinguish between those cells provided by the chip vendor as primitive cells (i.e., leaf candidates) and the user-defined hierarchy blocks built upon them. One way is to speak of a “cell library” vs. a “design library” as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a standard cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design.
The initial cell library is usually provided by a chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term “NAND” for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND. When a particular 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip. A single name is sufficient when dealing only in the context of a single user function.
The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are typically added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy is often a single block that defines the entire design, and the bottom layer of the hierarchy typically includes leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library.
Two common methods for specifying the design are schematic capture and hardware description languages. The schematic capture method provides a sophisticated user interface that allows a logic circuit to be drawn in graphical form on a computer display. Typically, the design is drawn using symbols from the cell and design libraries.
Encoding the design in a hardware description language (HDL) is a more common design entry technique for specifying modern integrated circuits. Hardware description languages are specifically developed to aid designers in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way. Often, the circuit is specified at the register transfer level (also known as a “behavior level”). The register transfer level description is often specified in terms of relatively small building blocks, the names of which are specified by the circuit designer.
For designs using HDL entry, the generation of a detailed description (or gate-level description) is often accomplished using logic design synthesis software. Logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Constituent parts of new gate-level logic created during each pass through the logic design synthesis software are typically given computer-generated component and net names. Each time the logic design synthesis software is executed, the component and net names that are generated by the software, and not explicitly defined by the user, may change depending on whether new logic has been added to or deleted from the integrated circuit design. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors are detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description.
In some design processes, the output of the logic design synthesis software is optimized by a logic optimizer tool, typically implemented in software. The logic optimizer tool can often create more efficient logic in terms of space, power or timing, and may remove logic from the design that is unnecessary. This action also typically affects the component and net names generated by the logic synthesis tool.
The output of the logic optimizer tool is an optimized detailed description that completely specifies the logical and functional relationships among the components of the design. Once the design has been converted to this form, it is necessary to verify that the logic definition is correct and that the circuit implements the function expected by the designer. If errors are detected or the resulting functionality or timing is unacceptable, the designer modifies the design as needed. As a result of each revision to the design, the logic design synthesis-generated component and net names may again change. These design iterations, however
Kerzman Joseph Peter
Rezek James Edward
Crompton Seager & Tufte LLC
Dinh Paul
Johnson Charles A.
Smith Matthew
Starr Mark T.
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