Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
1999-10-26
2002-11-12
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S502000
Reexamination Certificate
active
06480968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and an apparatus for transmitting a packet of data to a digital network.
2. Description of the Related Art
It is known to transmit packets of data through a digital network such as an IEEE1394 serial bus. When a slave station intends to transmit packets of data to the network, the slave station informs a master station of its intention. Normally, the master station periodically transmits a cycle start packet to the network in response to the information fed from the slave station. The period of repetitive transmission of the cycle start packet is equal to a time interval of 125 &mgr;s which is referred to as a nominal cycle. The slave station captures every cycle start packet. The slave station sequentially transmits isochronous packets of data to the network in response to the captured cycle start packets. In the case where the slave station has a temporary memory in a data flow path, a long delay time tends to occur before the transmission of isochronous packets of data is started.
Japanese published unexamined patent application 9-130655 discloses an image pickup apparatus including an imaging device for converting a picked-up image to an analog signal. In the apparatus of Japanese application 9-130655, an A/D converter changes the analog signal to a digital signal. In addition, a signal processing means converts the digital signal to a video signal. A transmission/reception circuit transmits the video signal in a serial format. Then, a system timing generating means operates the imaging device synchronously with a timing signal for driving the transmission/reception circuit. Accordingly, the data transmission rate of the output signal of the imaging device and the data transmission rate of the output signal of the transmission/reception circuit are matched to each other.
In the apparatus of Japanese application 9-130655, the video signal transmitted from the transmission/reception circuit has a sequence of 1-line-corresponding segments each having a start sync signal, an effective 1-line video data piece, and an end sync signal temporally arranged in that order.
In the case where the apparatus of Japanese application 9-130655 is connected with a communication system prescribing a data transmission rate which differs from the original data transmission rate determined by the transmission/reception circuit, it is necessary to provide a data-rate matching circuit.
SUMMARY OF THE INVENTION
It is a first object of this invention to provide an improved method of transmitting a packet of data to a digital network.
It is a second object of this invention to provide an improved apparatus for transmitting a packet of data to a digital network.
A first aspect of this invention provides a method comprising the steps of a) sequentially outputting data, and outputting a timing signal related to the data; b) producing a packet from the data outputted by the step a); c) temporarily storing the packet produced by the step b), and outputting the packet; d) detecting a specified relative timing within a duration of the packet which is being stored by the step c) in response to the timing signal outputted by the step a); and e) receiving the packet outputted by the step c), and transmitting the packet during a first nominal cycle after the step d) detects the specified relative timing.
A second aspect of this invention provides a method comprising the steps of a) sequentially outputting data, and outputting a timing signal related to the data; b) sequentially producing packets from the data outputted by the step a); c) temporarily storing the packets produced by the step b), and sequentially outputting the packets; d) detecting a specified relative timing within a duration of each packet which is being stored by the step c) in response to the timing signal outputted by the step a); e) incrementing a first packet number when the step d) detects the specified relative timing; f) deciding whether the first packet number incremented by the step e) is equal to or different from a second packet number at a start of every nominal cycle; g) receiving a packet outputted by the step c), and transmitting the received packet during a nominal cycle having a start at which the step f) decides that the first packet number is different from the second packet number; and h) incrementing the second packet number when the transmission of the packet by the step g) is completed.
A third aspect of this invention is based on the second aspect thereof, and provides a method wherein the step d) comprises counting pulses of a pixel-corresponding clock signal in the timing signal outputted by the step a), and generating a signal representing a horizontal address in accordance with the number of the counted pulses; comparing the horizontal-address signal with a first reference signal representing a predetermined horizontal address, and outputting a first identity-indicating signal when the horizontal-address signal is equal to the first reference signal; counting pulses of a horizontal sync signal in the timing signal outputted by the step a), and generating a signal representing a vertical address in accordance with the number of the counted pulses; comparing the vertical-address signal with a second reference signal representing at least one predetermined vertical address, and outputting a second identity-indicating signal when the vertical-address signal is equal to the second reference signal; and detecting a timing at which both the first identity-indicating signal and the second identity-indicating signal are outputted as the specified relative timing.
A fourth aspect of this invention provides a packet transmission apparatus comprising an information source sequentially outputting data, and outputting a timing signal related to the data; a packet generator producing a packet from the data outputted by the information source; a FIFO memory temporarily storing the packet produced by the packet generator, and outputting the packet; first means for detecting a specified relative timing within a duration of the packet which is being inputted into the FIFO memory in response to the timing signal outputted by the information source; and second means for receiving the packet outputted by the FIFO memory, and transmitting the packet during a first nominal cycle after the first means detects the specified relative timing.
A fifth aspect of this invention provides a packet transmission apparatus comprising an information source sequentially outputting data, and outputting a timing signal related to the data; a packet generator sequentially producing packets from the data outputted by the information source; a FIFO memory temporarily storing the packets produced by the packet generator, and sequentially outputting the packets; first means for detecting a specified relative timing within a duration of each packet which is being inputted into the FIFO memory in response to the timing signal outputted by the information source; second means for incrementing a first packet number when the first means detects the specified relative timing; third means for deciding whether the first packet number incremented by the second means is equal to or different from a second packet number at a start of every nominal cycle; fourth means for receiving a packet outputted by the FIFO memory, and transmitting the received packet during a nominal cycle having a start at which the third means decides that the first packet number is different from the second packet number; and fifth means for incrementing the second packet number when the transmission of the packet by the fourth means is completed.
A sixth aspect of this invention is based on the fifth aspect thereof, and provides a packet transmission apparatus wherein the first means comprises a horizontal address generator for counting pulses of a pixel-corresponding clock signal in the timing signal outputted by the information source, and generating a signal representing a horizontal address in accordanc
Shinohara Toshiaki
Tsuzuki Kengo
Butler Dennis M.
Matsushita Electric - Industrial Co., Ltd.
Woo Louis
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