Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2001-08-02
2004-12-14
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C713S401000, C710S033000
Reexamination Certificate
active
06832277
ABSTRACT:
1. FIELD OF THE INVENTION
The present invention generally relates to methods of transferring data between a data-transmitter and a data-receiver. More specifically, the invention relates to data-transmitters, data-receivers, and methods of broadcasting data onto a bus that reduce effective capacitive coupling (and data errors resulting from such capacitive coupling) between parallel interconnects during such data transfers.
2. BACKGROUND
In modern microprocessors, large numbers of interconnect wires, i.e., electrical conductors, connect various circuits. Many of these electrical conductors, such as metal traces in integrated circuits, run parallel for significant distances, and are therefore subject to noise from capacitive coupling. Such parallel metal traces may be on a single metallization layer within an integrated circuit. Alternatively, such parallel metal traces may be on different metallization layers within an integrated circuit. Capacitive coupling between parallel electrical conductors can create significant time delays. In addition, as discussed in U.S. Pat. No. 6,189,133 to Durham et al., capacitive coupling of parallel electrical conductors may result in false signal transitions in dynamic and self-timed circuits if the electrical conductors exceed 300 to 500 &mgr;m in length.
Thus, it could be desirable to provide a method and apparatus for avoiding capacitive coupling of parallel electrical conductors.
3. SUMMARY OF INVENTION
One embodiment of the invention is a data-transmitter for transmitting data. The data-transmitter includes a data-driving circuit. The data-driving circuit can output a first plurality of data values via a first plurality of data-output ports and can output a second plurality of data values via a second plurality of data-output ports. The data-transmitter also includes a plurality of data-delay circuits. Each of the inputs of the plurality of data-delay circuits is coupled to one of the second plurality of data-output ports. The data-transmitter also includes a plurality of electrical conductors. Each of the plurality of electrical conductors is coupled to one of the first plurality of data-output ports.
Another embodiment of the invention is a data-transmitter for transmitting data. The data-transmitter includes a data-driving circuit. The data-driving circuit can output a first plurality of data values via a first plurality of data-output ports and can output a second plurality of data values via a second plurality of data-output ports. The data-transmitter also includes a clock-delay circuit. The input of the clock-delay circuit is coupled to the first plurality of data-output ports and can strobe the first plurality of data-output ports. The output of the clock-delay circuit is coupled to the second plurality of data-output ports and can strobe the second plurality of data-output ports.
Still another embodiment of the invention is a data-receiver for receiving data. The data-receiver includes a plurality of data-delay circuits. The data-receiver also includes a plurality of electrical conductors and a data-receiving circuit. The data-receiving circuit includes a first plurality of data-input ports and a second plurality of data-input ports. The first plurality of data-input ports can receive, sample, and store a first plurality of data values. The second plurality of data-input ports can receive, sample, and store a second plurality of data values. Each of the outputs of the plurality of data-delay circuits is coupled to one of the first plurality of data-input ports of the data-receiving circuit. Each of the plurality of electrical conductors is coupled to one of the second plurality of data-input ports of the data-receiving circuit.
Yet another embodiment of the invention is another data-receiver for receiving data. This data-receiver includes a clock-delay circuit. The clock-delay circuit can delay a clock signal and can output a delayed-clock signal. The data-receiver also includes a first plurality of data-ports. The first plurality of data-ports can receive a first portion of data. The first plurality of data-ports is coupled to the second plurality of data-ports and can be strobed by the clock signal. The data-receiver also includes a second plurality of data-ports. The second plurality of data-ports can receive a second portion of data. The second plurality of data-ports can be strobed by the delayed-clock signal.
Still another embodiment is a method of broadcasting N, an even integer, bits of data onto a bus that includes a first plurality of electrical conductors and a second plurality of electrical conductors. The method includes: broadcasting a first portion of data that includes N/2 bits of data onto the first plurality of electrical conductors. Then, after a time period has elapsed that is greater than 0 seconds and less than the time period required to transfer 2 bits of data sequentially on one of the first plurality of electrical conductors, broadcasting a second portion of data that includes N/2 bits of data onto the second plurality of electrical conductors.
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“The impact of timing on linearizability in counting networks” by M. Mavronicolas, M. Papatriantafilou and P. Tsigas (abstract only).*
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Durham Christopher M.
Patel Parsotam T.
Park Vaughan & Fleming LLP
Ray Gopal C.
Sun Microsystems Inc.
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