Method and apparatus for translating an effective address to a r

Details Method and apparatus for translating an effective address to a r Method and apparatus for translating an effective address to a r

1998-03-16

2000-07-11

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

365 49, 711208, 711220, G06F 1200

Patent

active

06088763&

ABSTRACT:
A method and apparatus for translating an effective address to a real address within a cache memory are disclosed. As disclosed, a content-addressable memory contains a multiple of addresses, and each of these addresses is individually associated with a unique tag. The content-addressable memory also includes an input circuit, a logic circuit, and an output circuit. The input circuit is for receiving a first number and a second number that are utilized to access the content-addressable memory. The logic is circuit is for determining whether or not there is a match between one of the tags and the two numbers, in accordance with a mismatch expression. The output circuit is for generating an address associated with a tag which matches the two numbers, in accordance with the mismatch expression.

REFERENCES:
patent: 4730266 (1988-03-01), Meerbergen et al.
patent: 5600583 (1997-02-01), Bosshart et al.
patent: 5619446 (1997-04-01), Yoneda et al.
patent: 5644521 (1997-07-01), Simpson
patent: 5812521 (1998-09-01), Levenstein et al.
patent: 5875121 (1999-02-01), Yetter
Heal et al., "64-KByte Sum-Addressed-Memory Cache with 1.6-ns Cycle and 2.6-ns Latency" IEEE Journal of Solid State Circuits, vol. 33, No. 11, pp. 1682-1689, Nov. 1998.
Hang et al., "Leading-Zero Anticipatory Logics for Fast Floating Addition with Carry Propagation Signal", IEEE Transactions, pp. 385-388, 1997.
Cortadella et al., "Evaluation of A+B=K Conditions without Carry Propagation", IEEE Transactions on Computers, vol. 41, No. 11, pp. 1484-1488, Nov. 1992.
Cortadella et al., "Evaluating `A+B=K` Conditions in Constant Time", IEEE Transactions on Computers, pp. 243-246, 1988.
D. J. Kinniment, "An Evaluation of Asynchronous Addition", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 4, No. 1, pp. 137-140, Mar. 1996.
Khalid et al., "Digital Design of Higher Radix Quaternary Carry Free Parallel Adder", IEEE Transactions, pp. 187-189, 1997.
Lee Et Al., "Address Addition and Decoding Without Carry Propagation," IEICE Trans. Inf. & System, vol. E80-D, No. 1, Jan. 1997; pp. 98-100.

Affiliated with

Also associated with

Rating

Method and apparatus for translating an effective address to a r does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for translating an effective address to a r, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for translating an effective address to a r will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-552795