Method and apparatus for transistor sidewall salicidation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate

Reexamination Certificate

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C438S635000, C438S637000

Reexamination Certificate

active

07151018

ABSTRACT:
A method for manufacturing a transistor is provided. The transistor has a substrate with an insulator on the substrate. A structure on the insulator having a structure sidewall is provided with spacers covering a portion of the structure sidewall. An exposed portion of the structure sidewall is activated, and a conformal layer of metal or metal containing material is deposited on the exposed portion of the structure sidewall. The metal or metal containing material is annealed to diffuse into the exposed portion of the structure sidewall to form a salicide.

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B. Doyle, B. Boyanov, S. Datta, M. Doozy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau. Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout, PowerPoint Presented at the 2003 Symposia of VLSI Technology and Circuits, printed from Intel Website: www.intel.com.
Sergey Lopatin. Electrochemical metallization of nanostructures: Integrated circuits and micro-electro-mechanical systems. Recent Res. Devel. Electrochem, 6(2003): 57-100 ISBN: 81-7895-107-X.

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