Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-03-29
2011-03-29
Chery, Mardochee (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S108000, C711S121000, C711SE12001, C711SE12040, C711SE12020
Reexamination Certificate
active
07917698
ABSTRACT:
Embodiments of the present invention provide a system that handles load-marked and store-marked cache lines. Upon asserting a load-mark or a store-mark for a cache line during a given phase of operation, the system adds an entry to a private buffer and in doing so uses an address of the cache line as a key for the entry in the private buffer. The system also updates the entry in the private buffer with information about the load-mark or store-mark and uses pointers for the entry and for the last entry added to the private buffer to add the entry to a sequence of private buffer entries placed during the phase of operation. The system then uses the entries in the private buffer to remove the load-marks and store-marks from cache lines when the phase of operation is completed.
REFERENCES:
patent: 6463522 (2002-10-01), Akkary
patent: 7206903 (2007-04-01), Moir et al.
patent: 7484080 (2009-01-01), Chaudhry et al.
patent: 2004/0162951 (2004-08-01), Jacobson et al.
Chaudhry Shailender
Cypher Robert E.
Chery Mardochee
Jones Anthony P.
Oracle America Inc.
Park Vaughan Fleming & Dowler LLP
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