Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1999-07-09
2002-05-07
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C711S156000
Reexamination Certificate
active
06385716
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of microprocessors providing MMX™ instructions, and more particularly to register file coherence in such microprocessors.
2. Description of the Related Art
The Intel Architecture™ (IA) originally provided integer instructions that operate on a set of integer registers referred to collectively as an integer register file. Early IA processors were complemented by external floating point processors, such as the 80287™ and 80387™ processors, which execute floating point instructions. These floating point processors included their own floating point register file, also referred to as the floating point register stack due to the manner in which floating point instructions reference individual registers within the floating point register file. In particular, the x 87 architecture includes 8×80-bit floating point registers
100
, as shown in FIG.
1
A. With the advent of the 80486™, the floating point unit was integrated into the processor itself along with the floating point register file.
Finally, the Pentium™ provided media enhancement technology, otherwise known as MMX instructions. These instructions provide enhanced performance for operations typically performed in multimedia applications, such as video and audio calculations. The MMX instructions operate on an 8×64-bit MMX register file
200
, as shown in FIG.
1
B. However, for compatibility reasons discussed below, the 8 MMX registers are mapped, or aliased, onto the 8 floating point registers
300
, as shown in FIG.
2
. That is, from a programming perspective, the floating point and MMX register files comprise the same registers. Thus, a write of a value by an MMX instruction to register MM
6
followed by a read by a floating point instruction of register FP
6
would yield the value written by the MMX instruction.
The main reason for the design decision not to provide an architecturally separate MMX register file was to maintain compatibility with existing IA architecture operating systems, such as UNIX™, OS/2™ or Windows™. When performing task switches, these operating systems must save the state of the processor, which includes saving to memory the contents of both the integer and floating point register files. The addition of an architecturally distinct MMX register file would require the undesirable modification of already existing operating systems.
One result of the evolution of the
1
A described above is that programmers have developed certain conventions that they follow when developing software applications that employ floating point or MMX instructions. One convention is to mix floating point and MMX instructions only at the module or procedure level and to avoid mixing them at the instruction level. That is, programmers typically will code an entire procedure or module using only MMX (and integer instructions) without floating point instructions, or vice versa, rather than mixing MMX and floating point instructions in the same procedure. A switch from a floating point to an MMX instruction, or vice versa, is referred to as an instruction boundary. Thus, applications programmers typically attempt to minimize the number of instruction boundaries in their software applications.
A second convention is to leave all the floating point registers empty at the end of a section of floating point code (i.e., the tag bits of the floating point registers indicate they are empty), such as at the end of a floating point procedure. A third convention is similar to the second: leaving all the MMX registers empty at the end of an MMX procedure. The third convention is typically accomplished via the EMMS (empty multimedia state) instruction.
FIG. 3
shows a sample segment of source code illustrating an instruction boundary and use of the EMMS instruction.
FIG. 3
will be described in more detail below in the discussion of FIG.
7
.
As discussed previously, the MMX and floating point units of an IA microprocessor share the floating point register file architecturally. However, connecting both a floating point
402
and an MMX unit
404
to floating point register file
300
, as shown in
FIG. 4
, is costly in terms of wiring within a microprocessor
400
, potentially resulting in an increase in the number of layers required for implementation. Therefore, it has been observed that including a physically distinct MMX register file
502
, as shown in
FIG. 5
which is transparent to the programmer may provide some cost and performance advantages.
However, including a separate transparent MMX register file creates a problem. As discussed above, the IA requires the floating point and MMX registers programmatically to occupy the same space. Therefore, coherence, i.e., consistency of content, between the floating point and MMX register files must be maintained. As stated above, if an MMX instruction writes a value to MM
6
and a subsequent floating point instruction reads FP
6
, the same value must be returned as was written.
One way to achieve this coherence is to write to both register files on each write operation, regardless of whether the write instruction is a floating point or MMX instruction. However, this solution is disadvantageous in that it may require a larger amount of power and result in lower performance than simply writing to the specified register set.
Therefore, what is needed is an improved method and apparatus for tracking the coherence between the floating point and MMX register files that takes advantage of the conventions adopted by software application programmers.
SUMMARY
To address the above-detailed deficiencies, it is an object of the present invention to provide a method and apparatus for tracking coherence between distinct floating point and MMX register files in a microprocessor. Accordingly, in the attainment of the aforementioned object, it is a feature of the present invention to provide an apparatus that detects instruction boundaries between floating point and MMX instructions in a program executed by a microprocessor having distinct floating point and MMX register files. The apparatus includes a storage element that stores a previous instruction type indicating whether a previous instruction was a floating point instruction or an MMX instruction and an instruction translator coupled to the storage element. The translator receives an instruction, generates a current instruction type indicating if the instruction is a floating point instruction or an MMX instruction and compares the current instruction type with the previous instruction type. If the current instruction type and the previous instruction type are not the same, then the translator generates a signal indicating that the floating point and MMX register files are incoherent.
An advantage of the present invention is that it enables the microprocessor to have distinct floating point and MMX register files and yet maintain coherence between them. Another advantage of the present invention is that it enables the microprocessor to restore coherence between the distinct register files only upon encountering an instruction boundary between floating point and MMX instruction, a condition that typically occurs relatively infrequently.
In another aspect, it is a feature of the present invention to provide a microprocessor that tracks coherence between its distinct floating point and MMX register files. The microprocessor includes a floating point register file coupled to a floating point unit and an MMX register file coupled to an MMX unit. The microprocessor also includes a storage element that stores a previous instruction type indicating whether a previous instruction was a floating point instruction or an MMX instruction and an instruction translator coupled to the storage element and to the floating point and MMX units. The translator receives an instruction, generates a current instruction type indicating if the instruction is a floating point instruction or an MMX instruction and compares the current instruction type with the previ
Henry G. Glenn
Loper, Jr. Albert J.
Coleman Eric
Davis E. Alan
Huffman James W.
IP-First L.L.C.
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