Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-28
2003-03-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06530071
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to configuration of programmable logic devices, and more particularly to addressing defects in programmable logic devices using runtime parameterizable logic cores.
BACKGROUND
Field programmable gate arrays (FPGAs), first introduced by Xilinx in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability and high speed. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
As with most semiconductor devices, the size of FPGAs is limited by the quality of the manufacturing process. Because there are typically a number of flaws distributed across a wafer, the manufacturing yield for larger devices is much less than the yield for smaller devices. Thus, larger devices tend to be very expensive. While advances in manufacturing technology has increased yields for both large and small devices, yields can be further enhanced using techniques for tolerating manufacturing defects. The ability to tolerate defects in semiconductor devices has the potential for both increasing manufacturing yields and increasing the feasibility of manufacturing larger devices.
Hardware and software approaches have been suggested for tolerating defects in semiconductor devices. For example, one hardware approach uses redundant circuitry to make “spare parts” available on the device. However, providing redundant circuitry increases the device size, thereby reducing yields.
The software approach maps circuitry around defective areas of the device. One disadvantage to the software approach is that the software is typically computationally intensive, and the software would have to be rerun on the design for each device in order to map around defects.
Defect tolerance techniques for FPGAs have been explored, but the techniques have not been widely adopted. Since testing devices is expensive and there is a lack of suitable software for tolerating defects, an FPGA is usually discarded when the first defect is encountered in testing the FPGA.
An example run-time approach to defect tolerance is described in “Dynamic fault tolerance in FPGAs via partial reconfiguration,” by Emmert et al., IEEE Symposium on Field-Programmable Custom Computing Machines, April 2000. This paper describes a technique for automatically detecting faults in an operating FPGA circuit and reconfiguring the circuit around any detected defects. This approach addresses the problems associated with long runtimes of tools by bypassing the design tools. A circuit is remapped incrementally at the device level by keeping spare device resources available at design time. Emmert's approach does not provide control to the designer over the remapping process.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
In various embodiments, a method and apparatus are provided for tolerating defects in a programmable logic device (PLD). A PLD generally includes a plurality of configurable logic elements and interconnect resources. If one or more of the configurable logic elements and resources have circuit defects, the PLD may still provide a workable circuit with use of the present invention.
In the various embodiments of the invention defect tolerance is addressed at the logic core/application level. A design program is executed that includes executable code that both specifies a circuit design and generates a configuration bitstream that implements the circuit design on the programmable logic device. The design program also includes code that selectively skips the configurable logic elements and resources that contain the defects. In various embodiments, an individual configurable logic element, an entire row, or an entire column of elements can be skipped responsive to an input parameter from the designer. Thus, a designer can control how the design is implemented when defects are encountered, and a defect tolerant implementation can be generated quickly. This supports defect tolerance in a production environment, an in-system reconfiguration application, as well as a run-time reconfiguration application.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.
REFERENCES:
patent: 4845633 (1989-07-01), Furtek
patent: 5946219 (1999-08-01), Mason et al.
patent: 6078736 (2000-06-01), Guccione
John M. Emmert, Dinesh Bhatia; “Incremental Routing in FPGAs”; ASIC Conference 1998; Eleventh Annual IEEE International Proceedings; Rochester, NY; Sep. 13-16, 1998; pp. 217-221.
Vijay Kumar, Anton Dahbura, Fred Fischer, Patrick Juola; “An Approach for the Yield Enhancement of Programmable Gate Arrays”; 1989 International Conference on Computer-Aided Design; Nov. 5, 1989; pp. 226-229.
Steven A. Guccione, Delon Levi; “Run-Time Parameterizable Cores”; Field Programmable Logic and Applications (9th International WKSP); Aug. 30, 1999; pp. 215-222.
Emmert et al., “Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration”, IEEE Symposium on Field-Programamble Custom Computing Machines, Apr. 17-19, 2000, Preliminary Proceedings, pp. 1-10.
Guccione Steven A.
Sundararajan Prasanna
LeRoy D. Maunu Crawford PLLC
Levin Naum
Siek Vuthe
Xilinx , Inc.
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