Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2005-01-11
2005-01-11
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S219000, C712S248000, C712S221000, C712S228000, C719S332000, C718S108000
Reexamination Certificate
active
06842848
ABSTRACT:
Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and utilizing the stored value to control the instruction issuance sequence. For example, each of a plurality of hardware thread units of the multithreaded processor may include a corresponding local register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions. A global register arrangement may also or alternatively be used. The processor may be configured so as to permit the instruction issuance sequence to correspond to an arbitrary alternating even-odd sequence of threads, without introducing blocking conditions leading to thread stalls.
REFERENCES:
patent: 5339415 (1994-08-01), Strout et al.
patent: 5404469 (1995-04-01), Chung et al.
patent: 5613114 (1997-03-01), Anderson et al.
patent: 5649135 (1997-07-01), Pechanek et al.
patent: 5659785 (1997-08-01), Pechanek et al.
patent: 5682491 (1997-10-01), Pechanek et al.
patent: 5742840 (1998-04-01), Hansen et al.
patent: 6079010 (2000-06-01), D'Arcy et al.
patent: 6128720 (2000-10-01), Pechanek et al.
patent: 6151683 (2000-11-01), Wookey
patent: 6230251 (2001-05-01), Batten et al.
patent: 6256725 (2001-07-01), Batten et al.
patent: 6260189 (2001-07-01), Batten et al.
patent: 6269437 (2001-07-01), Batten et al.
patent: 6282585 (2001-08-01), Batten et al.
patent: 6317821 (2001-11-01), Batten et al.
patent: 6341338 (2002-01-01), Dennie
C. J. Glossner, “The Delft-Java Engine,” Doctoral Thesis, Delft University of Technology, Netherlands, Nov. 5, 2001.
“Basic Features of the HEP Supercomputer,” -ee.eng.hawaii.edu/˜nava/HEP/introduction.html, pp. 1-2.
“The MOVE Concept,” ce.et.tudelft.nl/MOVE/section3.2.html, pp. 1-2.
“Simultaneous Multithreading Project,” .cs.washington.edu/research/ smt/index.html, pp. 1-7.
“Introduction to Multithreading, Superthreading and Hyperthreading,” arstechnica.com/paedia/h/hyperthreading/hyperthreading-1.html, pp. 1-5.
Glossner C. John
Hokenek Erdem
Moudgill Mayan
Pan Daniel H.
Sandbridge Technologies Inc.
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