Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-11-18
2001-07-10
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S145000, C711S206000
Reexamination Certificate
active
06260131
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of computer systems, and more specifically, to controlling the timing and order of the execution of memory instructions in certain regions of computer memory to allow for increased processor efficiency.
2. Description of the Related Art
Current computer systems typically employ a hierarchical memory structure to facilitate the processing of memory access operations. This design practice evolved as an approach to minimize the processing delay and accompanying performance penalty that can occur while the processor is waiting for data or instructions (collectively, “memory operands”) to be provided from memory, while still supplying a large physical storage space. Even in very sophisticated computers, processing can come to a complete halt (a “stall”) until the memory request is serviced. Memory-related stalls may range from a few nanoseconds to several seconds, depending upon the computer's memory design, the storage location of the memory operand, and the memory access method. Designers adopted the hierarchical approach because a properly designed and managed hierarchical memory arrangement can minimize processor stalls and improve performance, without sacrificing system cost, size, or power requirements.
A commonly employed memory hierarchy is shown in FIG.
1
. This design approach includes a special, high-speed memory, known as a cache, in addition to main memory and a swap space. In this hierarchical memory system, the main memory is effectively a cache for the much slower swap space storage. While the cache near the CPU is generally controlled by hardware in the CPU, the main memory is a software-controlled cache. In this discussion, unless otherwise specified, the term “cache” will always refer to the hardware-controlled cache, and the term “main memory” will always refer to the software-controlled main memory.
In a hierarchical memory design, memory operands can be dynamically shifted among swap space, main memory, and cache to ensure that the operand is provided to the processor as quickly as possible (i.e, from cache) as often as possible. This memory control function is handled by a memory management system that is commonly implemented in both hardware and software (the “memory manager”). The hardware portion of the memory manager is known as the memory management unit (MMU), and may be implemented within the processor, or it may be a separate component, either integrated on the same silicon as the processor or on an entirely different integrated circuit that interfaces with the processor and memory.
FIG. 2
illustrates both the hardware and software portions of a typical memory management system. For clarity, portions of the memory management system not directly relevant to this discussion are not shown.
Referring to
FIG. 2
, memory management unit (MMU)
122
is shown within processor
120
. MMU
122
interfaces with bus interface unit
123
, which accesses main memory
131
and the system's I/O devices
132
via the system bus
133
. Hardware components of the MMU
122
that are relevant to this discussion include the translation lookaside buffer (TLB)
126
and the TLB miss handler
125
. Other memory management system hardware components and software functions include the load queue
127
and the store queue
128
, both shown in
FIG. 2
as implemented in the processor hardware, and the page miss handler (PMH)
124
and page table
129
, shown in
FIG. 2
in a typical software implementation.
Extending the hierarchical memory design approach resulted in the concept of “virtual memory,” and the separation of a memory operand's “address” from its physical location in memory. Virtual memory is an abstraction that is used to handle three primary tasks in a computer system: (1) memory hierarchy abstraction; (2) memory protection; and (3) memory fragmentation. Virtual memory was originally conceived as a way to apply the hardware-based concept of a hierarchical memory to software; i.e., allowing software to control and use main memory as a cache for the storage space that is implemented in large, slow magnetic or optical media. Using the concept of virtual memory, an operating system (OS) can create the illusion of an accessible memory space that is much larger than the actual main memory size implemented in DRAM in the hardware. The OS maps portions of the external physical storage space (the disk drives or other storage media) into main memory, and then swaps only those blocks of the storage space currently needed into main memory (hence the term “swap space”). Swap space is also sometimes referred to as paging space, and the blocks of memory that are swapped in and out of main memory are often called pages.
Since the most recently accessed pages also contain the memory operands that are likely to be accessed soon, the OS ensures that the most recently accessed pages are available to the processor in relatively fast DRAM. Therefore, the apparent latency of the large amount of accessible memory is quite low, compared to what the latency would be if all accesses went to the hard disk or other external storage media. A programmer can write his program assuming that he has much more memory available than is implemented in DRAM on the system on which the program is running.
The amount of memory apparently available to a program is dependent upon the OS. Although the OS may create a very large amount of virtual memory, it may only allow a particular program to use a portion of the virtual memory space. If the OS supports multitasking, then it must partition and assign the virtual memory space to each of the concurrent processes. Memory protection and fragmentation are two tasks that are a necessary part of the OS's memory partitioning and assignment function. The OS protects a process's assigned memory by insuring that it cannot be corrupted by another concurrent process. Protecting memory from corruption in this manner increases system reliability.
The OS also keeps track of memory fragments actually used by a process and “stitches together” those fragments such that the process is unaware that it is actually using anything other than a contiguous block of memory. In other words, the OS does not actually assign contiguous blocks of memory to each process, because such an approach would likely result in nonuse of a large portion of assigned memory. Instead, the OS assigns available, non-contiguous fragments of virtual memory, and translates the programmer's view of his address space (sometimes called an effective address space or linear address space) to the address space represented by the assigned fragments. While the programmer's effective address space is contiguous, the virtual addresses that the OS assigns to those effective addresses may not be contiguous. This memory fragmentation function increases system efficiency by insuring that limited memory space is not wasted by being assigned and protected but unused.
To access a memory operand, the processor must take the programmer's effective address, translate it to a virtual address (the address within the large virtual memory space), and then finally, translate the virtual address into a physical address (the address within the main memory space). The physical address can then be used to access either the hardware controlled SRAM cache or the DRAM main memory.
The primary focus of this discussion is the translation from virtual to physical address. The virtual address consists of a virtual page number, plus an offset. The virtual page number identifies the relevant page of virtual memory, and the offset identifies the storage location of the operand on the page. Similarly, a physical address consists of a page frame number, plus an offset. Like the virtual page number, the page frame number identifies the appropriate block of SRAM or DRAM, and the offset identifies the actual storage location within the identified memory block.
The main structure used for the virtual address to
Blomgren James S.
Kikuta Betty Y.
Potter Terence M.
Booth Mathew J.
Booth & Wright, L.L.P.
Intrinsity, Inc.
Nguyen Hiep T.
Wright Karen S.
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