Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-04
2004-05-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C714S033000, C714S733000
Reexamination Certificate
active
06735746
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the fields of Computer-Aided Design (CAD), and test code for design and test of digital computer processor circuits. The invention particularly relates to CAD programs for converting existing testcases to operate on new members of a processor. The invention specifically relates to conversion of testcases having Translation Lookaside Buffer (TLB) initialization or references.
BACKGROUND OF THE INVENTION
The computer processor, microprocessor, and microcontroller industries are evolving rapidly. Many processor integrated circuits marketed in 2002 have ten or more times the performance of the processors of 1992. It is therefore necessary for each manufacturer to continually design new products if they are to continue producing competitive devices.
Testcases
When a design for a new processor integrated circuit is prepared, it is necessary to verify that the design is correct through design verification. It is known that design verification can be an expensive and time-consuming process. It is also known that design errors not found during design verification can not only be embarrassing when they are ultimately discovered, but provoke enormously expensive product recalls.
Design verification typically requires development of many test codes. These test codes are often prepared by highly paid engineers and are therefore expensive to develop. Each test code is then run on a computer simulation of the new design. Each difference between the computer simulation of a test code and expected results is analyzed to determine whether there is an error in the design, in the test code, in the simulation, or in several of these. Analysis is expensive as it is often performed manually by highly paid engineers.
Typically, the test codes are constructed in a modular manner. Each code has one or more modules, each intended to exercise one or more particular functional units in a particular way. Each test code incidentally uses additional functional units. For example, a test code intended to exercise a floating point processing pipeline in a full-chip simulation will also use instruction decoding and memory interface (including Cache Memory and Translation Lookaside Buffer) functional units. Similarly, a test code intended to exercise integer execution units will also make use of memory interface functional units.
The simulation of the new design on which each test code is run may include simulation of additional “off-chip” circuitry. For example, this off-chip circuitry may include system memory. Off-chip circuitry for exercising serial ports may include loopback multiplexors for coupling serial outputs to serial inputs, as well as serializer and deserializer units.
The combination of test code with configuration and setup information for configuring the simulation model is a testcase.
It is known that testcases should be self-checking; as they must often be run multiple times during development of a design. Each testcase typically includes error-checking information as necessary to verify correct execution.
Once a processor design has been fabricated, testcases are often re-executed on the integrated circuits. Selected testcases may be logged and incorporated into production test programs.
Memory Hierarchy
Modern high-performance processors implement a memory hierarchy having several levels of memory. Each level typically has different characteristics, with lower levels typically smaller and faster than higher levels.
A Cache Memory is typically a lower level of a memory hierarchy. There are often several levels of cache memory, one or more of which are typically located on the processor integrated circuit. Cache memory is typically equipped with mapping hardware for establishing a correspondence between cache memory locations and locations in higher levels of the memory hierarchy. The mapping hardware typically provides for automatic replacement (or eviction) of old cache contents with newly referenced locations fetched from higher-level members of the memory hierarchy. This mapping hardware often makes use of a cache tag memory. For purposes of this application cache mapping hardware will be referred to as a tag subsystem.
Many programs access memory locations that have either been recently accessed, or are located near recently accessed locations. These locations are likely to be found in fast cache memory, and therefore more quickly accessed than other locations. For these reasons, it is known that cache memory often provides significant performance advantages.
Most modern computer systems implement virtual memory. Virtual memory provides one or more large, continuous, “virtual” address spaces to each of one or more executing processes on the machine. Address mapping circuitry is typically provided to translate virtual addresses, as used by the processes to access location in “virtual” address spaces, to physical memory locations in the memory hierarchy of the machine. Typically, each large, continuous, virtual address space is mapped to one or more, potentially discontinuous pages in a single physical memory address space. This address mapping circuitry often incorporates a Translation Lookaside Buffer (TLB).
A TLB typically has multiple locations, where each location is capable of mapping a page, or other portion, of a virtual address space to a corresponding portion of a physical memory address space.
New Processor Designs
Many new processor integrated circuit designs have similarities to earlier designs. New processor designs are often designed to execute the same, or a superset of, instruction set of an earlier processor. For example, and not by way of limitation, some designs may differ significantly from previous designs in memory interface circuitry, but have similar floating point execution pipelines and integer execution pipelines. Other new designs may provide additional execution pipelines to allow a greater degree of execution parallelism than previous designs. Yet others may differ by providing for multiple threads or providing multiple processor cores in different numbers or manner than their predecessors; multiple processor or multiple thread integrated circuits may share one or more levels of a memory hierarchy between threads. Still others may differ primarily in the configuration of on-chip I/O circuitry.
Many manufactures of computer processor, microprocessor, and microcontroller devices have a library of existing testcases originally written for verification of past processor designs.
It is desirable to re-use existing testcases from a library of existing testcases in design verification of a new design. These libraries may be extensive, representing an investment of many thousands of man-hours. It is known, however, that some existing testcases may not be compatible with each new processor design.
Adaptation of existing testcases to new processor designs has largely been a manual task. Skilled engineers have reviewed documentation and interviewed test code authors to determine implicit assumptions and other requirements of the testcases. They have then made changes manually, tried the modified code on simulations of the new designs, and analyzed results. This has, at times, proved expensive.
Adapting Testcases
It is desirable to automate the process of screening and adapting existing testcases to new processor designs.
In a computer system during normal operation, TLB entries are dynamically managed by an operating system kernel.
During design verification of a processor or multiprocessor integrated circuit, it is generally desirable to limit the scope of many individual testcases to simplify debugging. For that reason, most testcases are run without an operating system kernel; and therefore often contain particular TLB entries as part of their setup information, or may contain code that directly addresses TLB locations.
Some testcases, including but not limited to testcases that test for interactions between successive operations in pipelines, are particularly sensitive to execution timing. These testcases may include p
Maly John W.
Thompson Ryan C.
Hewlett--Packard Development Company, L.P.
Rossoshek Helen
Smith Matthew
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