Method and apparatus for timing control in a memory device

Details Method and apparatus for timing control in a memory device Method and apparatus for timing control in a memory device

1995-12-18

1997-09-02

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

36518901, 36518907, G11C 700, G11C 800

Patent

active

056639252

ABSTRACT:
In a memory device such as a DRAM or multiport DRAM, each of a plurality of memory cells includes an access transistor with a gate connected to a word line and a storage capacitor with a storage node connected through the access transistor to a digit line. Data is transferred on the digit line to and from the storage capacitor when the word line is activated and the access transistor enabled thereby. According to the present invention, a timing control circuit is provided to control deactivation of the word line. The timing control circuit includes a digit-write/transfer model that simulates a read-write cycle in a DRAM or a serial write transfer operation in a multiport DRAM. The digit-write transfer model produces an output signal indicating the state of the modeled data transfer operation. The timing control circuit also includes a reference voltage circuit and a level comparator. The level comparator compares the model output signal to the reference voltage provided by the reference voltage circuit. The level comparator includes a sensitive analog multi-stage current mirror differential amplifier circuit and produces a signal input to a RAS timing chain circuit which deactivates the word line upon completion of the modeled data transfer operation.

REFERENCES:
patent: 4322825 (1982-03-01), Nagami
patent: 4502140 (1985-02-01), Proebsting
patent: 4947374 (1990-08-01), Wada et al.
patent: 4998222 (1991-03-01), Sussman
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5490114 (1996-02-01), Butler et al.
patent: 5513143 (1996-04-01), McClure

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