Method and apparatus for timing adjustment

Details Method and apparatus for timing adjustment Method and apparatus for timing adjustment

2007-09-18

2007-09-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000

Reexamination Certificate

active

11269741

ABSTRACT:
A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

REFERENCES:
patent: 5930182 (1999-07-01), Lee
patent: 6318707 (2001-11-01), Hara et al.
patent: 6335885 (2002-01-01), Shimizu
patent: 7233533 (2007-06-01), Lee
patent: 2004/0044919 (2004-03-01), Dabral
patent: 2004-185608 (2004-07-01), None

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