Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-04-24
2001-05-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06230300
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique of distributing a clock signal to elements of a semiconductor integrated circuit, and particularly, to a method and apparatus for optimizing a depth of a tree network for clock distribution with minimal power consumption.
2. Description of the Prior Art
Improvements in semiconductor technology have developed large-scale, high-speed semiconductor integrated circuits. These circuits have many elements that must receive clock signals whose frequencies are increasing these days.
Synchronous systems realize correct operation timing on elements by synchronizing the operation timing in response to rising edges and falling edges of a clock signal. Ideally, all elements in a semiconductor integrated circuit which need a clock signal must receive it without delay. Actually, the clock signal received by the elements involves delay due to the resistance and capacitance of the metal lines used to distribute the clock signal to the elements. If two elements which are controlled by the same clock signal are at different distance from the clock root driver, they will receive the clock signal at different times. This arrival time differential is called skew. A large skew spoils synchronism in the operation of the elements, and therefore, the skew must be minimized by reducing the delay.
An H-tree network for distributing a clock signal to elements of a semiconductor integrated circuit was proposed by S. Dhar et al in “Reduction of clock delays in VLSI structures,” Proc. IEEE Int. Conf. on Computer Design, 1984. Improved H-tree networks are disclosed in Japanese Patent Application Publication Nos. 3-030721 and 3-137851.
The H-tree networks usually employ multistage buffering to reduce delay in distributing a clock signal. The multistage buffering arranges buffer cells at nodes in several stages of an H-tree network in a semiconductor integrated circuit, so that a clock signal is distributed from a root driver to elements of the integrated circuit through the buffer cells. In the multistage buffering, first-stage buffer cells drive second-stage buffer cells, the second-stage buffer cells drive third stage buffer cells, and so on. Last-stage buffer cells directly drive each of the elements which are grouped. Each group contains at least one of elements. In each group of elements, no H-tree is formed, and the elements are connected to one another through shortest wiring. Such a group of elements is sometimes called a “cluster.”
However, the prior arts mentioned above give no consideration on power consumption of an H-tree networks.
To reduce power consumption of a clock distribution network, J. Cong et al proposed a technique of optimizing the size of buffer cells, i.e., the gate length and width of each CMOS transistor, or the width of the metal lines that carry the clock signal to the elements, in “Simultaneous Driver and Wire Sizing for Performance and Power Optimization,” Proc. IEEE Int. Conf. on CAD, 1994. The objective of this prior art, however, is an H-tree network without multistage buffering, and therefore, the prior art is inapplicable to H-tree networks employing multistage buffering.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method and apparatus for easily and quickly calculating the optimum depth of a tree network for distributing a clock signal to elements of a semiconductor integrated circuit, so that the tree network may work with minimum power.
Another object of the present invention is to provide a method and apparatus for speedily calculating the optimum depth of a tree network for distributing a clock signal to elements of a semiconductor integrated circuit without a knowledge of skilled designers, thereby reducing the development period and manufacturing cost of semiconductor devices.
In order to accomplish the objects, the present invention provides a method for optimizing a tree depth of an H-tree network for distributing a clock signal to elements of a semiconductor integrated circuit. The principle of the method is shown in FIG.
6
. The method includes the steps of (a) entering parameters, (b) defining a short circuit current component PS, cell internal switching current component PI, and switching current of interconnect capacitance component PW of power consumption of the H-tree network with equations employing a tree depth m as a variable, (c) defining the power consumption F of the H-tree network as the sum of the components PS, PI, and PW, and (d) finding a tree depth that minimizes the power consumption F. The parameters set in the step (a) are those needed to define the components PS, PI, and PW with the tree depth m, for instance, an inclination coefficient K related to short circuit currents and the total number N of the elements to receive the clock signal. The parameters K and N are described later.
The short circuit current component PS is expressed as follows:
PS=K×(C0/2
m
)×(N/2
m
)×f×V
2
where m is the tree depth, K is the inclination coefficient, C0 is total load capacitance estimated as the sum of the capacitance of shortest wiring for supplying the clock signal to the elements and the load capacitance of input terminals of the elements, N is the total number of the elements, f is the frequency of the clock signal, and V is a source voltage.
The cell internal switching current component PI is expressed as follows:
PI=BPWR×2
m
×f×V
2
where m is the tree depth, BPWR is the cell internal switching current per the frequency of the clock signal of each buffer cell through which the clock signal is supplied to a corresponding group of the elements, f is the frequency of the clock signal, and V is the source voltage.
The switching current of interconnect capacitance component PW is expressed as follows:
PW=((A×2
(m/2)−1
−1)×L×Cunit+2
m
×Cin)×f×V
2
where m is the tree depth, L is an averaged side length of a rectangular area in which the elements are distributed, Cunit is the capacitance of a unit length, Cin is the load capacitance of an input terminal of each element, A is a wiring length coefficient depending on the tree depth m, f is the frequency of the clock signal, and V is the source voltage.
The step (d) differentiates the power consumption F of the H-tree network, i.e., the sum of the components PS, PI, and PW with respect to the tree depth m as ∂F/∂m and finds the tree depth that minimizes the power consumption F by solving the following equation:
∂F/∂m=0
In this way, the present invention easily finds the optimum tree depth that minimizes the power consumption F of the H-tree network presented as the sum of the components PS, PI, and PW without a knowledge of skilled designers, thereby reducing the designing and developing periods and manufacturing costs of semiconductor devices.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.
REFERENCES:
patent: 5410491 (1995-04-01), Minami
patent: 5557779 (1996-09-01), Minami
patent: 6006025 (1999-12-01), Cook
patent: 5-54100 (1993-03-01), None
Do Thuan
Foley & Lardner
Kabushiki Kaisha Toshiba
Smith Matthew
LandOfFree
Method and apparatus for the optimization of a tree depth... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for the optimization of a tree depth..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for the optimization of a tree depth... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2441979