Method and apparatus for the operational verification of a micro

Details Method and apparatus for the operational verification of a micro Method and apparatus for the operational verification of a micro

1996-12-05

1998-04-14

Canney, Vincent P.

Excavating

39518301, G06F 1100

Patent

active

057401837

ABSTRACT:
Presented are a method an apparatus for operational verification of a microprocessor subject to an interrupt during a "target" activity. A software model of the microprocessor allows determination of the start and end of the target activity via one or more signals generated during the target activity. A testing program causes the microprocessor model to produce a timing signal (i.e., a trigger event) a number of system clock cycles (i.e., a delay time) before the target activity begins. A software memory model coupled to the microprocessor model includes an interrupt signal generator. The interrupt signal generator receives the trigger event and generates an interrupt signal after the delay time expires following the trigger event. A simulation trace obtained during a first "characterization" procedure is used to determine the delay time. Following the characterization procedure, the microprocessor replaces the microprocessor model. Execution of the testing program by the microprocessor causes the interrupt to occur during the target activity, and causes the microprocessor to produce a test result. The test result is compared to an expected result to determine proper operation. The microprocessor model and the memory model are contained within a memory unit of a microprocessor testing system during testing. The microprocessor testing system includes a central processing unit (CPU), chip set logic, a system bus, and a memory bus in addition to the memory unit.

REFERENCES:
patent: 4998250 (1991-03-01), Kohlmeier et al.
patent: 5321828 (1994-06-01), Phillips et al.

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