Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Utility Patent
1999-01-06
2001-01-02
Tran, Andrew (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S438000, C438S510000, C438S511000, C438S514000, C438S528000
Utility Patent
active
06168981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices.
2. Discussion of the Related Art
As is known in integrated circuit technology it is often necessary to electrically insulate some regions of the chip from others. For example, in a VIP circuit the driving circuit must be insulated from the power transistor.
One technique used for insulation is function insulation. However, this technique unavoidably forms parasitic transistors which ultimately define the actual operating limits of the entire structure of the integrated circuit.
FIG. 1
illustrates a typical structure of a MOSFET power transistor circuit. The MOSFET structure typically comprises a substrate
1
, doped with impurities of the N
+
type, which acts as a drain terminal of the MOSFET device. An epitaxial layer
2
of the N
−
type is grown on the substrate
1
. Two regions
3
a
and
3
b
of the P
+
type, known as deep-body regions, are located in the epitaxial layer. Above the respective deep-body regions
3
a
and
3
b
there are body regions
4
a
and
4
b
which are doped with P-type impurities. Two source regions, respectively
5
a
and
5
b
for the body region
4
a
, and
5
d
and
5
c
for the body region
4
b
, are accommodated in each one of the body regions
4
a
and
4
b.
An oxide layer
10
a
is located above the adjacent edges of the body regions
4
a
and
4
b
, and the polysilicon gate
6
a
is placed on layer
10
a
. The gate
6
a
is covered by a dielectric layer
7
a
, which is preferably a chemical vapour deposited oxide, such as P-Vapox. Gate terminals
6
b
and
6
c
, having related oxides
10
b
and
10
c
and dielectric layers
7
b
and
7
c
, are located at the edges of the body regions
4
a
and
4
b.
Finally, the entire structure is covered with a layer of metal, preferably aluminum, which makes contact with the body regions
4
a
and
4
b
and with the source regions
5
a
,
5
b
,
5
c
, and
5
d
This structure includes parasitic transistors which limit its operation. The emitters, bases and collectors of these parasitic transistors are respectively the sources
5
a-d
, the deep-body regions
3
a
and
3
b
or body regions
4
a
and
4
b
, and the drain, which is constituted by the substrate
1
. The emitters, bases and collectors of the parasitic transistor comprise their active regions. One of these parasitic transistors is shown in FIG.
1
and is designated by the reference numeral
9
. The emitter of the transistor
9
is constituted by the source region
5
d
, the base is constituted by the body/deep-body region
3
b
, and the collector is constituted by the substrate
1
. It is evident that there are at least three other parasitic transistors which are present with the source/deep-body/drain combinations. They have not been illustrated for the sake of simplicity. The following three methods may be used to reduce the gain of the parasitic transistor
9
. First, the deep-body region
3
b
, i.e. the base of the transistor, may be doped heavily. Secondly, the source
5
d
and the deep body
3
b
or the body
4
b
, i.e. the emitter and the base of the transistor
9
, are shorted. Third, the source
5
d
may be manufactured as short as possible, within the limits of the photolithographic technology available.
Despite these methods, when the PMOS is on there is a voltage drop in the deep-body portion underlying the source. A positive bias V
be
can thus be formed between the base and the emitter of the transistor
9
, turning he transistor on. The gain of this parasitic transistor increases as current and temperature increase, limiting the performance of the PMOS.
FIG. 2
illustrates a typical structure of an IGBT device. The structure of the IGBT is similar to the structure of the PMOS device of
FIG. 1
, except that there is an additional epitaxial layer
2
a
which is interposed between the epitaxial layer
2
and the substrate
1
and is doped with impurities of the N
+
type.
The IGBT device includes an NPN-type parasitic transistor
100
, the collector, base, and emitter of which are formed respectively by the source region
5
d
, the body/deep-body region
4
b
/
3
b
, and the epitaxial layer
2
or
2
a
. The effect of the transistor
100
combines with the effect of another parasitic transistor
11
of the PNP type, the collector, base, and emitter of which are respectively the body/deep-body
4
b
/
3
b
, the epitaxial layer
2
or
2
a
, and the substrate
1
. Of course other parasitic transistors can form in the other body/deep-body region.
The two parasitic transistors
100
and
11
constitute a thyristor. In order to avoid activating this thyristor it is necessary to reduce the gain of the two transistors so that &agr;
NPN
+&agr;
PNP
<1.
Two techniques are used to reduce the gain of the PNP transistor
11
. The first technique is the introduction of a buffer layer between the P-type substrate
1
and the N-type drain. This layer is heavily doped with N-type impurities. The second technique is to implant a lifetime killer metal, such as gold or platinum, which is then diffused to distribute it uniformly throughout the thickness of the wafer. The gain of the NPN transistor
100
is of course also reduced by this.
The operating conditions for which the above described parasitic components are particularly detrimental are, in the case of the PMOS (FIG.
1
), dynamic dV/dt and unclamped conditions. In the case of the IGBT device (FIG.
2
), static and dynamic latch-up are possible.
A third example of a power device in which parasitic transistors reside is a Vertical Intelligent Power device, better known as a VIP device.
FIG. 3
illustrates a typical structure of a VIP device.
The VIP device comprises an N
+
-type substrate
31
above which there is an N-typepe epitaxial layer
32
. The epitaxial layer
32
accommodates the P
+
-type buried layer
33
. The P
+
-type buried layer
33
accommodates the low-power control devices, typically a vertical NPN transistor
51
and a lateral PNP transistor
52
. The P
+
buried layer also acts as insulation for the low-power devices. The vertical NPN transistor
51
comprises a first N
+
-type buried layer
34
which is connected to a collector terminal
35
by means of a sinker region
36
which is also doped with N
+
-type impurities. The N
+
buried layer
34
and the N
−
type region
41
that accommodates the P
+
-type base
37
and the N
+
-type emitter
38
of the NPN transistor are surrounded by two P
+
-type insulation regions
39
and
40
. These insulation regions form, together with the P
+
buried layer
33
, an insulation well of the N region
41
.
Next to the vertical NPN transistor
51
is a lateral PNP transistor
52
. This transistor also includes an N
+
buried layer
42
which is connected to the base terminal
43
by means of a sinker region
44
. The N
−
type region
45
accommodates the emitter
46
and the collector
47
, both of which are of the P type, and is insulated by the insulation region
40
and an additional insulation region
48
. The insulation regions
39
,
40
and
48
, together with the P
+
buried layer, form a region that is termed the P-well.
The power device
53
comprises a base region
49
, which is connected to the base terminal
50
, and an emitter region
54
, which is connected to an emitter terminal
55
. The collector of the power device
53
is constituted by a metallic layer
30
which is connected to the substrate of the entire VIP device.
In the above described VIP structure, the low-power circuit (NPN transistor
51
and PNP transistor
52
) must be insulated from the power transistor
53
. The technique commonly used is junction insulation. However, this technique, as mentioned, unavoidably leads to the formation of parasitic transistors that limit the operation of the device.
The first example of a parasit
Battaglia Anna
Coffa Salvatore
Fallica Piergiorgio
Raineri Vito
Ronsisvalle Cesare
Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
Galanthay Theodore E.
Lebentritt Michael S.
Morris James H.
Tran Andrew
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