Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-11-30
2002-10-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06467073
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to forming connections within programmable interconnect matrices (PIMS) and between multi-stage PIMs generally and, more particularly to a method and/or architecture for automated generation of single-stage and multi-stage PIMs, preferably using an automatic router.
BACKGROUND OF THE INVENTION
Conventional approaches to forming connections within a PIM involve automated layout creation of one or more single stage PIMs. Conventional approaches use an array tiler to place a regular array of PIM bits. The PIM bits had fixed metal patterns within them. Following placement of the connections, an architecture specific program is written to calculate contact coordinates and place contacts over the PIM bits for programming.
Referring to
FIG. 1
, a flow diagram of such a conventional approach
10
is shown. The approach
10
comprises a state
12
, a state
14
and a state
16
. The state
12
creates PIM bit cells and feedthrough cells. The state
14
uses a memory compiler to tile PIM bit cells. The state
16
runs a program to place the contacts.
Such a conventional method does not allow input to span the PIM cell boundary. Additionally, such a method is limited to only those routing channels that physically cross the cell boundary or are built into the cell (i.e., only vias are placed). Such a method also does not support placement and connection of buffers or other cells.
More leaf cells are required to handle feed through routes and varying numbers of possible inputs per PIM bit throughout the PIM array. Development of additional cells is required for feedthroughs and for varying numbers of possible inputs per PIM bit. Using conventional approaches, input connections can not span PIM cell boundaries, which reduces the number of possible inputs per PIM bit and/or increase the overall PIM bit area.
Such conventional approaches may have the disadvantages of (i) being limited to a regular array of similar structures, (ii) having limited additional structures (such as buffers) since such structures can not be inserted into distinct locations within the PIM or the PIM boundaries and be automatically connected, (iii) not handling multi-stage PIMS, (iv) not defining a schematic generation method, and (v) requiring custom contact programming code for each PIM architecture.
Complex Programmable Logic Devices (CPLDs) and other programmable logic devices (which may include simple PLDs, FPGAs and ASICs) rely on PIMs (or similar interconnect paths) to route signals within the device. Manually determining the layouts (and/or schematics) for the connections within the PIM is a time consuming process.
SUMMARY OF THE INVENTION
The present invention concerns a method to automatically generate a single and/or multistage PIM, comprising the steps of (A) generating a schematic that matches a layout of the PIM, (B) optionally generating a first stage and a second stage for the PIM, depending on one or more electronic and/or physical properties of the PIM and (C) automatically placing and connecting a non-regular structure at an input and/or output of a stage of the PIM.
The objects, features and advantages of the present invention include providing an architecture and/or method that may allow (i) placing of non-regular structures such as buffers, drivers, logic gates or other cells (e.g., structures other than conductors, contacts, switches and/or other mux elements), into a PIM, (ii) defining of logical connectivity information by a PIM application, (iii) layout pinning that may define routing channels and connection points to a next level, (iv) automatic routing of signals and placing of the contacts, (v) schematic placing arrays of PIM bits with named wire connections as defined by the PIM application and/or (iv) layout pinning and automatic routing that may hierarchically create a single stage and/or multistage layout with or without additional buffers.
REFERENCES:
patent: 5477475 (1995-12-01), Sample et al.
patent: 5659484 (1997-08-01), Bennett et al.
patent: 6128770 (2000-10-01), Agrawal
patent: 6357305 (2002-03-01), Witt et al.
Cypress Semiconductor Corp.
Do Thuan
Maiorana P.C. Christopher P.
Siek Vuthe
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