Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-02
2001-09-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06295627
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to schemes for the automated design of memory devices and/or components thereof. In particular, the schemes described herein may be applied to develop a compiler that is useful during the design of memory arrays, the incorporation of redundancy logic and the design of semi-custom control logic and decoders of memory devices.
BACKGROUND
Modern integrated circuit designers are often confronted with the problem of developing new circuit/component designs in as short a time as possible in order to minimize product time to market. Although complicated, often this task becomes one of fitting a desired set of circuit components into as small an area as possible and arranging interconnecting conductors between those elements in a manner that minimizes the lengths of the conductive paths. To compound this problem, the design solution is usually subject to a minimum spacing geometry, dictated by the resolution limits (and other technology factors) of the fabrication process employed. When a designer develops a new circuit or component, he/she typically begins by creating a schematic for the design. Such design processes have been automated to some degree for a number of years and a typical schematic produced through such processes usually consists of symbols representing the basic units of the design connected together with signals (or nets—short for networks). The symbols are usually chosen from a library of parts that the designer draws upon to build the schematic. The interconnection of the symbols and the signals (e.g., as stored in a design database) creates the connections needed to specify the design such that a netlist can be derived from the connections. The netlist can then be used to create a simulation model of the design to verify its operation before the actual component is built.
The manner in which the schematic representation of the overall circuit is developed may vary depending upon whether fully custom or semi-custom circuit elements need to be employed in the design. Thus, circuit designers often begin by searching a standard library of circuit elements to see if any will match the new circuit's requirements. The search may begin at a relatively high level to determine whether any previously defined circuit elements satisfy the needed chip-level or lower level (called “cells”) architectures. The number of hierarchical levels of cell structure will depend on the nature and complexity of the circuitry being designed.
If matching cells are found, the designer can proceed to synthesize the circuit. Otherwise, the designer may be required to build semi-custom cells from available low-level cells. In the event no existing circuit elements can satisfy the necessary design requirements, the designer may be forced to develop custom solutions. For example, decoding logic used in memory devices are typically custom implementations. Once the circuit elements have been chosen, the circuit is synthesized and optimized for a given set of technology rules (i.e., the design rules that describe limitations of the fabrication processes to be used). Commercial computer programs for performing such routines are available and are commonly used to perform such tasks.
The netlist produced during the synthesis and optimization process can be used to provide the information needed by a routing software package to complete the actual design. The routing software will create the physical connection data to create the layer information needed for the component specified by the design. The resulting design may then be simulated to test its behavior and, if necessary, the design can be modified to meet target design goals.
Once a design has been approved through simulation, tape out may be ordered. In the tape out process, the symbolic representation of the circuit is translated into an actual layout using a commercial layout editor program. As with the synthesis programs, layout editors utilize tables of design rules that are specific to the ultimate manufacturing process to be used to produce computer-readable files (masks) that can be used in the fabrication of the integrated circuit.
This conventional design methodology is flawed in as much as it requires that the designer be familiar with the specifics of the design language used to specify the components of the design. As design languages evolve and are replaced by new languages, this forces designers to relearn these languages. Further, this design procedure becomes tedious when designers are faced with developing an entire family of components, individual units of which may share some similarities but likely differ in other regards. Moreover, although conventional simulation tools often perform better (i.e., provide results more quickly) when the underlying circuit design is specified in terms of a hierarchical data structure, most conventional design tools do not provide such output. Rather, conventional design tools tend to provide so-called “flattened” data structures. Thus, simulation times (and, hence, overall design times) are often unnecessarily long.
Further deficiencies of these conventional design processes are also apparent where the circuit being designed is a random access memory (RAM) device. Often, to improve the production yield of RAMs, it is necessary to add redundant rows or blocks in the memory core; this way, when a flawed row of memory cells is formed, the row can be replaced by a redundant row. However, it is difficult for the designer to gauge the impact of the inclusion of such redundancy features on the overall chip aspect ratio because conventional design tools do not allow for the easy inclusion of redundant elements.
SUMMARY OF THE INVENTION
In one embodiment, a method of generating a design, layout, schematic, netlist, abstract or other equivalent circuit representations (hereinafter “layout”) for a memory that may have redundant circuitry is provided. In general, a set of user inputs describing parameters of the layout is acquired through a graphical user interface. Based on these user inputs, or at least a subset thereof, one or more leaf cells is/are generated. Then using the leaf cells, a design database for the layout is generated from the user inputs. The design database reflects physical hierarchies of the layout and includes redundant circuitry when the memory contains at least 256 K bits and/or at least one of the user inputs meets or exceeds a predetermined value (or combination of predetermined values) for implementing the redundant circuitry. In some cases, the redundant circuitry may be a data and/or address path, parallel to a non-redundant data and/or address path within the layout. The above-mentioned parameters described by the user inputs may include an array size, a defect rate, and/or a leaf cell design, layout or schematic. This scheme may be embodied as a set of computer-readable instructions, for example to be executed by a computer system.
In a further embodiment, a method of producing a peripheral circuit layout that includes redundancy logic is provided. In this scheme variations of physical device hierarchies for the peripheral circuitry are automatically synthesized, based on lower level cell parameters of the device that embodies the peripheral circuit. In addition to automatically synthesizing the layout, the method may provide for automatically characterizing the layout. The parameters of the layout generally may include line width, line spacing, line length, gate width, transistor spacing, gate length, transistor length, resistivity, capacitance, and/or other physical or electrical device parameters. As before, this scheme may be embodied as a set of computer-readable instructions, for example to be executed by a computer system such as a workstation. The normal path(s) and the redundant path(s) can be tweaked (e.g., for speed) independently, if desired.
In yet another embodiment, an advanced graphical interface configured to allow a user to rearrange a memory array architecture by selecting one or more of a plurality o
Gowni Shiva P.
Patel Alpesh B.
Wang Bo B.
Cypress Semiconductor Corporation
Do Thuan
Smith Matthew
Wagner , Murabito & Hao LLP
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